An efficient AES implementation using FPGA with enhanced security features

Zodpe, Harshali; Sapkal, A. M.

doi:10.1016/j.jksues.2018.07.002

Cited by 73 publications

(59 citation statements)

References 14 publications

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“…In XC6VLX240T device, the proposed LAES improved the throughput by 202.98% and 65.11% compared to [24] and [30] respectively. Although the throughput in [25] is higher by 3.94%, the proposed LAES is better in terms of performance efficiency by 361.3% and has a lesser in area utilization by 79.05%. The throughput in [25] is higher using XC6SLX150 but in terms of area and performance efficiency, the proposed LAES is better by 84.42% and 444.53% respectively.…”

Section: Data Collection Analysis and Discussionmentioning

confidence: 94%

“…Although the throughput in [25] is higher by 3.94%, the proposed LAES is better in terms of performance efficiency by 361.3% and has a lesser in area utilization by 79.05%. The throughput in [25] is higher using XC6SLX150 but in terms of area and performance efficiency, the proposed LAES is better by 84.42% and 444.53% respectively. In XC4VLX60 device, there is an increase in throughput by 42.28% and 6.97% compared to [30] and [25] respectively.…”

Section: Data Collection Analysis and Discussionmentioning

confidence: 94%

“…In the XC7VX690T device, the proposed LAES is 78.79% better in terms of throughput and an improvement of 1.37% in performance efficiency compared to [30] although the proposed design has a higher area by 76.34% in slice usage. Similarly compared to [25], although there is an increase in area by 22.96% in slice utilization, there is an improvement of 41.71% in throughput and 15.26% in performance efficiency. In XC6VLX240T device, the proposed LAES improved the throughput by 202.98% and 65.11% compared to [24] and [30] respectively.…”

Section: Data Collection Analysis and Discussionmentioning

confidence: 95%

“…The result of the synthesis on various devices is presented in Table II. Area utilization for FPGAs is identified with respect to number of slices [20], [25]. Throughput signifies the number of bits processed per unit time and is specified in Gbps or Mbps.…”

Section: Data Collection Analysis and Discussionmentioning

confidence: 99%

“…In the paper of [25], a modified S-box and an improved key generation for initial key required for encryption using PN Sequence Generator was introduced. The developed AES with proposed modifications resulted to a significant improvement in throughput after the design is synthesized on various FPGA devices.…”

Section: Related Literaturementioning

confidence: 99%

See 4 more Smart Citations

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

Acla¹,

Gerardo²

2019

IJRTE

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 Abstract: Advanced Encryption Standard (AES) is one of the most secured encryption algorithm because of its robustness and complexity. Because of its complexity, AES has slow computation. This paper presents a Lightweight Advanced Encryption Standard (LAES) design by replacing the MixColumn transformation of the traditional AES with a 128-bit permutation to lessen its computational complexity. Implementation of hardware cryptographic encryption aims to find the best trade-off between throughput and resource utilization. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and achieves the maximum clock frequency of 480.50 MHz with the highest throughput of 6.15 Gbps when synthesized on Virtex 7 XC7VX690T. The results on other devices show a higher throughput, better performance efficiency, and lesser area utilization when compared to the existing AES hardware implementation.

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Section: Data Collection Analysis and Discussionmentioning

confidence: 94%

Section: Data Collection Analysis and Discussionmentioning

confidence: 94%

Section: Data Collection Analysis and Discussionmentioning

confidence: 95%

Section: Data Collection Analysis and Discussionmentioning

confidence: 99%

Section: Related Literaturementioning

confidence: 99%

See 3 more Smart Citations

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

Acla¹,

Gerardo²

2019

IJRTE

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A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

Qureshi

Qayyum

Islam

et al. 2021

Circuit Theory & Apps

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Summary Technologies and new standards have converted the traditional networks and systems into new smart cities integrated networks. Different factors are behind to build these new networks in terms of hardware, software, standards, technologies, and infrastructure. Internet of things (IoT) is one of the popular network types based on small and portable devices. Some of the IoT applications are more critical and sensitive like smart healthcare systems wherein time data delivery is needed without any delay. Keeping in view the criticality of such applications, this study proposes a secure storage, processing and transmission (SSPT) technique. This technique is based on two modules named Advanced Encryption Standard (AES) in Electronic Code Book (ECB) mode and AES in Ciphered Message Authentication Code (CMAC) mode. In the first module, the AES is implemented in ECB mode to provide encryption to IoT computer vision data. In the second module, the AES is integrated with the CMAC algorithm to provide encryption, integrity, and authentication. The said modules are implemented in a field programmable gate array (FPGA) device which acts as a secure edge computing device. The SSPT is verified by the test vectors given by international standards such as the National Institute of Standards and Technologies (NIST) and Federal Information Processing Standards (FIPS) which are adaptable, proficient, and vigorous as compared to previous techniques.

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Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

Renugadevi

Thangallapally²,

Vemula³

et al. 2022

Security and Privacy

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With the majority of users migrating to a cloud computing platform, the responsibility for data security has increased considerably. As data with various levels of sensitivity moves out of the confines of the system firewall, there is no control over where it resides; it depends on the cloud server being used. This makes the use of secured cryptographic algorithms necessary to improve data security and maintain the confidentiality of data. The encryption algorithm used most extensively today is the Advanced Encryption Standard (AES). Hardware acceleration with Field Programmable Gate Array can improve the performance of AES. This study examines various approaches for improving data encryption methods that can be utilized as hardware accelerators to improve the fundamental AES cipher. Some research publications suggest ways to boost throughput while others advise ways to save area and power. Many subsequent developments have also used other cryptographic methods such as RSA and ECC to improve key management security. This study examines the outcomes of multiple ways for metrics including throughput, area, power, and data security, and explains some of the best implementation solutions for each metric individually.

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An efficient AES implementation using FPGA with enhanced security features

Cited by 73 publications

References 14 publications

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

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