An efficient algorithm for library-based cell-type selection in high-performance low-power designs

Abstract

In this paper, we present a complete framework for celltype selection in modern high-performance low-power designs with library-based timing model. Our framework can be divided into three stages. First, the best design performance with all possible cell-types is achieved by a Minimum Clock Period Lagrangian Relaxation (MinClock LR) method, which extends the traditional LR approach to conquer the difficulties in discrete scenario. Min-Clock LR fully leverages the prevalent many-core systems as the main body of its workload is composed of independent tasks. Upon a timing-valid design, we solve the timing-constrained power optimization problem by min-cost network flow. Especially, we identify and address the core issues in applying network flow technique to library-based timing model. Finally, a power prune technique is developed to take advantage of the residual slacks due to the conservative network flow construction. Experiments on ISPD 2012 benchmarks show that on average we can save 13% more leakage power on designs with fast timing constraints compared to start-of-theart techniques. Moreover, our algorithm shows a linear empirical runtime , finishing the largest benchmark with one million cells in 1.5 hours.

Maximizing yield in Near-Threshold Computing under the presence of process variation

“…We compare our approach NTC against an Non-NTC (!NTC) multi-V th gate-sizing method proposed by Li et al [30]. Their approach achieved competitive results against solutions obtained from the ISPD 2012 design contest [26] and [27].…”

“…Each design was optimized in accordance to industrial imposed each benchmark (col. 2); the achieved delays (1000 instances) when considering PV (col. 3); and adjusted target clock with PV for using [30] (col. 4).…”

Gate Sizing Under Uncertainty

“…Several approaches exist that address continuous and discrete gate sizing. Common methods to solve the gate sizing problem have been convex optimization [4], Lagrangian Relaxation [2,3], [17], and gradient and sensitivity-based optimization [9], [18].…”

“…A drawback of this approach, however, is that a potentially new critical path may emerge. This remains to be a major challenge for existing gate sizing techniques that attempt to maintain delay accuracy during optimization [9], [17], [18]. To address this issue, the frequency of delay updates can be increased by adjusting M and γ to be larger values, as we have done.…”

A temperature-aware synthesis approach for simultaneous delay and leakage optimization

“…The gate width is adjusted to achieve various drive strengths, enabling circuit power and timing trade-offs. In the discrete domain, gate sizing is an NP-Hard problem [5] and several well known solutions have been proposed, such as Lagrangian relaxation [20], dynamic programming [2], combinatorial relaxation [9], and sensitivity-based optimizations [3][4] [7][21]. Dual threshold voltage (V t ) combined with gate sizing has also been proposed [8].…”