An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms

Bonfietti,; Benini,; Lombardi,; Milano,

doi:10.1109/date.2010.5456924

Cited by 39 publications

(35 citation statements)

References 7 publications

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“…Other implementation aspects such as storage space or communication delays can be modeled in a similar manner in the dataflow graph. These methods are beyond the scope of this paper; interested readers are referred to for example [9], [26], [27]. Figure 3 illustrates an example behavior of the SADF model of the full WLAN application mapped onto a reconfigurable platform, as discussed in detail below.…”

Section: Modeling Applications Withmentioning

confidence: 99%

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Predictable dynamic embedded data processing

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Basten³

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration; formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

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Section: Modeling Applications Withmentioning

confidence: 99%

“…[9] uses constraint solving to find solutions that satisfy requirements, [10] is based on SAT solving techniques. Both approaches determine throughput optimal mappings using static, single-rate models.…”

Section: Related Workmentioning

confidence: 99%

Predictable dynamic embedded data processing

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Stuijk

Basten³

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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“…This is done to ensure that the actors with higher criticality are allocated to resources with higher computational power (resources with higher nominal operating points are on average faster). In the second part of the algorithm (lines [11][12][13][14][15][16][17][18][19], allocation optimization is performed. The allocation of each actor in increasing order of criticality is reconsidered.…”

Section: B Heuristic Algorithmmentioning

confidence: 99%

“…There has been extensive research in the area of task allocation and scheduling for MPSoC [6]- [10], [13]- [15]. The researchers in [10], [14], [15] proposed methods to map throughput-constrained applications modeled as SDFGs to the resources in a MPSoC. None of them, however, considers the impact of process variation.…”

Section: Introductionmentioning

confidence: 99%

“…RELATED WORK Several techniques have been proposed to minimize process variation at the circuit and microarchitectural levels [1], [12], but they are unable to hide the variation at the system level. There has been extensive research in the area of task allocation and scheduling for MPSoC [6]- [10], [13]- [15]. The researchers in [10], [14], [15] proposed methods to map throughput-constrained applications modeled as SDFGs to the resources in a MPSoC.…”

Section: Introductionmentioning

confidence: 99%

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Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

Mirzoyan

Åkesson

Goossens

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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A bs tr act -As t echnology s cales , t he impact of proces s variat ion on the maximum supported frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result in a significant loss in yield, defined as the number of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for real-time streaming applications modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications. The three main contributions of this paper are: 1) Using data flow graphs that are well-suited for modeling and analysis of real-time streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding. 2) We present two approaches for optimizing the yield. The approaches give different results at different costs. 3) We present exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of real applications, and are compared to the mapping methods that are unaware of hardware variation. Our results demonstrate yield improvements of up to 50% with an average of 31%, showing the effectiveness of our approaches.

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Combining Analytical and Simulation-Based Design Space Exploration for Efficient Time-Critical and Mixed-Criticality Systems

Herrera

Sander

2014

Lecture Notes in Electrical Engineering

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In the context of the design on time-critical systems, analytical models with worst case workloads are used to identify safe solutions that guarantee hard timing constraints. However, the focus on the worst case often leads to unnecessarily pessimistic and inefficient solutions, in particular for mixed-critical systems. To overcome the situation, the paper proposes a novel design flow integrating analytical and simulation-based Design Space Exploration (DSE). This combined approach is capable to find more efficient design solutions, without sacrificing timing guarantees. For it, a first analytical DSE phase obtains a set of solutions compliant with the critical time constraints. Search of the Pareto optimum solutions is done among this set, but it is delegated to a second simulation-based search. The simulation-based search enables more accurate estimations, and the consideration of a specific (or an averagecase) scenario. The chapter shows that this can lead to different Pareto sets which reflect improved design decisions with respect to a pure analytical DSE approach, and which are found faster than through a pure simulation-based DSE approach. This is illustrated through an accompanying example and a proof-of-concept implementation of the proposed DSE flow.

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An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms

Cited by 39 publications

References 7 publications

Predictable dynamic embedded data processing

Predictable dynamic embedded data processing

Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

Combining Analytical and Simulation-Based Design Space Exploration for Efficient Time-Critical and Mixed-Criticality Systems

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