Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

Abstract

A bs tr act -As t echnology s cales , t he impact of proces s variat ion on the maximum supported frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result in a significant loss in yield, defined as the number of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for real-time streaming applications modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications. The three main contributions of this paper are: 1) Using data flow graphs that are well-suited for modeling and analysis of real-time streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding. 2) We present two approaches for optimizing the yield. The approaches give different results at different costs. 3) We present exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of real applications, and are compared to the mapping methods that are unaware of hardware variation. Our results demonstrate yield improvements of up to 50% with an average of 31%, showing the effectiveness of our approaches.

Throughput analysis and Voltage-Frequency Island partitioning for streaming applications under process variation

“…Mirzoyan et al [17] solve an application to MPSoC mapping problem for improved timing yield, considering the impact of process variation. We assume a specified mapping, and analyze the throughput of a system with VFI partitions.…”

“…Although, the presented models are inspired by the ones in [17], our modeling differs in the following ways. They model variation as a set of operating points (frequency values), but we explicitly model die-to-die and within-die variations by means of Probability Density Functions (PDF) of the maximum supported frequency of a resource (this is what is known from a statistical characterization).…”

“…To determine the mapping of the application to the platform (i.e. binding vector b), we used the variation-aware mapping algorithm given by Mirzoyan et al in [17]. The periodic static-order schedules s(r) for actors on shared resources are determined by the common list scheduler [15].…”

“…This assumption enables us to have fair results when estimating the impact of guard-band reduction on timing yield (a relaxed throughput requirement creates a large slack in performance). We use the approach in [17] and perform a mapping of the synthetic cyclic application to the platform for the specified 500 MHz frequencies, such that the throughput is maximized. The result is a throughput value, which is taken as the requirement.…”

Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs

“…The four main contributions of this work are (1) as an extension of Mirzoyan et al [2012], we differentiate best-effort, firm real-time and soft real-time application classes which require different optimization criteria. For best-effort and firm real-time applications, we maximize the average throughput over all manufactured chips and the yield, respectively.…”