An efficient and practical MOS statistical model for digital applications

Zhang, Q.; Liou, Juin J.; McMacken, J.; Stiles, K.; Thomson, J.; Layman, P.

doi:10.1109/iscas.2000.856357

Cited by 7 publications

(2 citation statements)

References 6 publications

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“…An industrial hardware-calibrated 65 nm CMOS technology transistor statistical models is used to investigate the effect of process variations on the proposed sensing, amplifier, and squaring circuits. In [32], [33], it has been demonstrated that the utilization of statistical transistor models is capable of accounting for both D2D and WID variations. A very good fitting with the measured data is reported in [32], [33], not only for the mean and standard deviation values, but also for the correlation between nMOS and pMOS transistors data.…”

Section: The Effect Of Process and Temperature Variations On The Pmentioning

confidence: 99%

“…In [32], [33], it has been demonstrated that the utilization of statistical transistor models is capable of accounting for both D2D and WID variations. A very good fitting with the measured data is reported in [32], [33], not only for the mean and standard deviation values, but also for the correlation between nMOS and pMOS transistors data. These statistical models are available in the design kits provided by STMicroelectronics.…”

Section: The Effect Of Process and Temperature Variations On The Pmentioning

confidence: 99%

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Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

Mostafa

Anis

Elmasry

2011

IEEE Trans. Circuits Syst. I

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Reliability and variability have become big design challenges facing submicrometer SRAM designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for NBTI aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on-chip analog controller. Postlayout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65 nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on the SRAM array. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB reduces the read failure probability from 0.32% to 0.05% and the SNM degradation from 10.9% to 2.6% at 10 years aging time. In addition, the proposed ABB enhances the soft errors immunity of the SRAM cell by reducing the critical charge degradation from 12.7% to 3.4% at 10 years aging time.Index Terms-Adaptive body bias, deep submicrometer, negative bias temperature instability, process variations, soft errors, SRAM cells.

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Section: The Effect Of Process and Temperature Variations On The Pmentioning

confidence: 99%

Section: The Effect Of Process and Temperature Variations On The Pmentioning

confidence: 99%

Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

Mostafa

Anis

Elmasry

2011

IEEE Trans. Circuits Syst. I

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A design-oriented timing jitter/skew model in voltage-to-time converter (VTC) circuits

Mostafa

Ismail

2014

Analog Integr Circ Sig Process

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A design oriented model for timing jitter/skew of Voltage-to-Time Converter (VTC) circuits

Mostafa

Ismail

2014

2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE)

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An efficient and practical MOS statistical model for digital applications

Cited by 7 publications

References 6 publications

Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

A design-oriented timing jitter/skew model in voltage-to-time converter (VTC) circuits

A design oriented model for timing jitter/skew of Voltage-to-Time Converter (VTC) circuits

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