An efficient compact test generator for I/sub DDQ/ testing

Fault models and test generation for IDDQ testing

“…The amount of IDDQ is dierent between input vector (0, 0) and (0, 1) when a resistive short between the output of 2-input NAND gate and GND exists [12]. In general, higher amount of IDDQ is induced when input vector (0, 0) is applied, because the output is connected to VDD with lower resistance, In [19], PODEM-based test generation is performed for input fault model. Input fault model is one of functional fault models of logic gates.…”

“…Reverse order simulation is a simulation technique with applying test vectors in the reverse order, i.e. the last generated test vector is applied rst [19,29]. This may m a k e earlier generated test vectors unnecessary.…”

“…Regeneration of test vectors based on essential fault information has been proposed in [19]. Essential fault is dened as a fault which is detected by N or less numb e r o f t e s t v ectors among a generated test set, where N is pre-specied.…”

A simple and efficient method for generating compact IDDQ test set for bridging faults

“…This paper proposes an efficient direct compaction method for IDDQ testing of bridging faults in combinational circuits. Recent previous work on compact tests for IDDQ testing of bridging faults in combinational circuits includes [2]- [4]. [2] and [3] are direct compaction methods, and [4] is a dynamic compaction method.…”

“…We do not consider the possibility of oscillation which occurs and may prevent the fault from being detected if there is an active signal path between the bridging two lines. (Basically, each compact test generation method by itself in [2], [3], and [4] also does not seem to handle the problem.) [2] reports that the loss of fault coverage due to the oscillation is small.…”