An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits

Leyn, F.; Gielen, Georges; Sansen, Willy

doi:10.1145/288548.288629

Cited by 19 publications

(22 citation statements)

References 8 publications

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“…The first kind of method is to find W by directly solving eqn (1) [3,4]. First-order models can be computed easily, since an explicit equation for W exists.…”

Section: Review Of the Opd Methodsmentioning

confidence: 99%

“…Hence, high-order models are necessary. Reference [3] suggests using the first-order solution as the starting point and then using SPICE-in-the-loop method to solve the equation. It also suggests scaling the variables to linearize strongly non-linear functions, which transforms eqn (1) to eqn (2).…”

Section: Review Of the Opd Methodsmentioning

confidence: 99%

“…Analog cell sizing methods can be classified into two main categories: width and length (W/L)-based methods [1,2] and operating-point driven (OPD)-based methods [3][4][5]. The former method uses the width and length as the design variables.…”

Section: Introductionmentioning

confidence: 99%

“…OPD-based method is used much less than width and length-based method in recent literatures. However, it has been reported that the OPD-based methods have distinct advantages [3][4][5], which can be summarized as follows. Firstly, it highly relieves the convergence problem of electrical simulators, as a DC consistent solution cannot be found for some W/L in the search space and these W/L are difficult to be pruned beforehand [3].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, W is calculated from device biases (voltages, currents) in OPD-based methods, which decreases the search space, because voltage / current biases and L have small ranges. Fourthly, OPDbased methods allow the designer to reason in terms of voltages and currents and relieve him from the burden of determining device sizes [3].…”

Section: Introductionmentioning

confidence: 99%

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A novel operating-point driven method for the sizing of analog IC

Liu

Pak

Zheng

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-It is known that the operating-point driven (OPD) analog sizing methods have clear advantages compared with the sizing methods of directly using transistor width and length as the decision variables. However, new analog sizing algorithms using OPD technique in modern technologies have seldom been reported in recent years. One of the main reasons is that with the scaling down of the technologies, the transistor models are much more complex, which makes the available DC root solving algorithms and the look-up-table-based methods face significant challenges on accuracy, efficiency and memory requirements. Instead of solving the equations to find the width of transistors, interpolating in a pre-constructed look-up-table, or using regression methods, a novel method, called on-line interpolation operating-point driven (OIOPD), is proposed. OIOPD finds the width of the transistor by the interpolation of the width-current curve with already determined length and voltage biases. The lower and upper points to decide the interpolated value are generated by on-line simulations using the two extreme values of the width in a technology. Experimental results in 0.25μm, 0.18 μm and 90nm technologies show that OIOPD has 10 times improvement on accuracy, 300-1100 times improvement on efficiency compared with the available methods. In addition, no extra memory (e.g. the memory to save the look-up table) is needed. These advantages make OIOPD suitable for operating-point driven analog sizing methods in modern technologies. A practical analog sizing example using OIOPD is also provided.

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“…The first kind of method is to find W by directly solving eqn (1) [3,4]. First-order models can be computed easily, since an explicit equation for W exists.…”

Section: Review Of the Opd Methodsmentioning

confidence: 99%

Section: Review Of the Opd Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A novel operating-point driven method for the sizing of analog IC

Liu

Pak

Zheng

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Automatic DC operating point computation and design plan generation for analog IPs

Iskander

Louërat

2007

Analog Integr Circ Sig Process

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DC operating point computation is inescapable for both knowledge-based and simulation-based analog synthesis. In this perspective, this article presents the automatic computation of DC operating point and the generation of suitable design plans for analog IPs. The analog IP is built as a hierarchy of subcircuits inside our dedicated framework CAIRO+. Leaf subcircuits are known as devices and higher-level subcircuits are known as modules. Each subcircuit is represented by a dependency graph. The dependency graph expresses electrical dependencies of circuit parameters on a selected set of design parameters. The dependency graph of the analog IP is constructed, in a hierarchical bottom-up approach, by merging graphs of children devices and modules. The graph is converted to a directed acyclic graph (DAG) by detecting and removing existing directed cycles. The resulting DAG is the design plan for the analog IP. Upon construction, the DAG is executed, in a top-down approach, to compute the DC operating point and the dimensions of the transistors. The computed DC operating point is compared to a DC simulation to ensure its correctness. The proposed methodology has been successfully applied to size and bias two analog IPs: a single-ended two-stage operational amplifier and a differential cascode current-mode integrator. The results prove the efficiency and accuracy of the proposed methodology.

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A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

Mendhurwar

Sundani

Aggarwal

et al. 2011

Analog Integr Circ Sig Process

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There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.

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An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits

Cited by 19 publications

References 8 publications

A novel operating-point driven method for the sizing of analog IC

A novel operating-point driven method for the sizing of analog IC

Automatic DC operating point computation and design plan generation for analog IPs

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

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