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is paper describes a new DC modeling methodology apphcable to CMOS integrated circuits. It is named operating point driven DCfomulation because the operating point is specified directly, and the device dimensions W and L are determined out of it. With other methods, one specifies the device dimensions }Vand L and determines the operating point. Our method is important for manual design because it rdlows the designer to reason in terms of voltages and currents and releaves hlm from the burden of determining device sizes. me algorithm is guaranteed to converge, and is computation~y efficient, which rdlows interactive design space exploration using optimization-based sizing. A design plan used in optimization-based sizing consists for the largest part out of solving the DC part. Speeding up the DC p& with a computationally efficient dgonthm, that allows parrdlelfisation, results in a boost of optimization speed.

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The task of a topology selector within an analog synthesis system is to find the best available analog circuit topology out of a library for a given set of input specifications. The IntroductionFor the synthesis of analog integrated circuits, an hierarchical design strategy is nowadays being used in most programs [1,2]. The design of higher-complexity modules (e.g. A/D converters) is translated into the design of smaller lowercomplexity circuits (e.g. comparator) and ultimately devices. In between each of the hierarchical levels the design process consists of several steps such as topology selection, circuit sizing, layout generation, extraction and verification. Topology selection has been recognized as the first of those consecutive steps.The goal of topology selection is to search through the set of candidate topologies in a library that implements the required circuit behavior and to find the topology that best matches the input performance specifications in the specified technology process. The set of input specifications can be provided either by a human designer who uses such a tool, or can be derived from a synthesis step at a higher hierarchical level in an automated analog synthesis system. The process can be repeated hierarchically in the sense that a topology is built up from lower -level blocks, for each of which later on in the design process again a lower-level topology has to be selected, and so forth.Although topology selection is an inherent part of analog synthesis, many programs published in the literature so far do not cover this problem. Programs that do handle it, such as OPASYN [3], OASYS [4], or the stand-alone tool HECTOR [5], use heuristic rules to decide between the different predefined alternatives. The selection between different related topologies in [6] has been integrated within the sizing process, by adding binary variables that control the topology configuration This research was part of a project with ESA-ESTEC (No9890/92/NL/GS) as additional optimization variables. However, none of these techniques makes explicit use of quantitative data about the obtainable performance ranges of the different candidate topologies to carry out the selection. The use of such information is, however, essential for the selection of a good topology, and the selection of a good topology is as important to obtain a highquality design solution (for the lowest power and area consumption) as the use of (global) optimization when sizing the selected topology afterwards. Our aim is to use quantitative performance space data to select the most promising topology candidate, which will then be sized by a separate sizing tool. The use of performance-space data also reduces the need for CPU-time-expensive redesign iterations -decreases the likelihood that a selected topology later on in the design process turns out not to be able to meet the input specifications.This paper introduces a topology selection composed of analytical filtering (based on boundary checking and interval analysis) and rule-b...