A flexible topology selection program as part of an analog synthesis system

Abstract

The task of a topology selector within an analog synthesis system is to find the best available analog circuit topology out of a library for a given set of input specifications. The IntroductionFor the synthesis of analog integrated circuits, an hierarchical design strategy is nowadays being used in most programs [1,2]. The design of higher-complexity modules (e.g. A/D converters) is translated into the design of smaller lowercomplexity circuits (e.g. comparator) and ultimately devices. In between each of the hierarchical levels the design process consists of several steps such as topology selection, circuit sizing, layout generation, extraction and verification. Topology selection has been recognized as the first of those consecutive steps.The goal of topology selection is to search through the set of candidate topologies in a library that implements the required circuit behavior and to find the topology that best matches the input performance specifications in the specified technology process. The set of input specifications can be provided either by a human designer who uses such a tool, or can be derived from a synthesis step at a higher hierarchical level in an automated analog synthesis system. The process can be repeated hierarchically in the sense that a topology is built up from lower -level blocks, for each of which later on in the design process again a lower-level topology has to be selected, and so forth.Although topology selection is an inherent part of analog synthesis, many programs published in the literature so far do not cover this problem. Programs that do handle it, such as OPASYN [3], OASYS [4], or the stand-alone tool HECTOR [5], use heuristic rules to decide between the different predefined alternatives. The selection between different related topologies in [6] has been integrated within the sizing process, by adding binary variables that control the topology configuration This research was part of a project with ESA-ESTEC (No9890/92/NL/GS) as additional optimization variables. However, none of these techniques makes explicit use of quantitative data about the obtainable performance ranges of the different candidate topologies to carry out the selection. The use of such information is, however, essential for the selection of a good topology, and the selection of a good topology is as important to obtain a highquality design solution (for the lowest power and area consumption) as the use of (global) optimization when sizing the selected topology afterwards. Our aim is to use quantitative performance space data to select the most promising topology candidate, which will then be sized by a separate sizing tool. The use of performance-space data also reduces the need for CPU-time-expensive redesign iterations -decreases the likelihood that a selected topology later on in the design process turns out not to be able to meet the input specifications.This paper introduces a topology selection composed of analytical filtering (based on boundary checking and interval analysis) and rule-b...

A CAD methodology for automatic topology selection & sizing

“…In addition, spice simulation run in the loop demands enormous time effort. While reported approaches [8]- [10] not only fail to take care of the imposing dc performances while evaluating the topologies but also lack of global optimizer yields suboptimal design. Analytical expressions of performance metrics of a given topology as developed in [11]- [13] are used in [8][9] but with changing technology information, analytical expressions of even existing topologies change thus requiring the models to be regenerated for every topology.…”

“…1/A v and 1/CMRR are simulated over the DoE and fitted into a model expressed by (10). Here y is the performance to be modeled, x i 's {i=1,2,...,p} are the design variables having inversely proportional relationship with the performance and z j 's {j=1,2,...,q} are the design variables which are directly proportional; c ij 's, c ijkl 's are the model coefficients.…”

Computer-aided design of analog and mixed-signal integrated circuits

“…This can for instance be done using interval analysis techniques [64] or using interpolation techniques in combination with adaptive sampling [65]. In all these programs, however, topology selection is a separate step.…”

“…Also, this step was automated using constraint programming techniques in the DONALD tool [80]. Together with a separate topology-selection tool based on boundary checking and interval analysis [64] and a performance-driven layout generation tool [81], all these tools are now integrated into the AMGIE analog circuit synthesis system [82] that covers the complete design flow from specifications over topology selection and circuit sizing down to layout generation and automatic verification. An example of a circuit that has been synthesized with this AMGIE system is the particle/radiation detector front end of Fig.…”

An analogue module generator for mixed analogue/digital asic design

“…5 The flow diagram of the topology selector is depicted in Figure 6. The filtering sequence is a combination of procedural and knowledge-based approaches and consists of the following filters: (i) a boundary-checking filter that checks whether the specifications are within the feasible intervals for each individual performance characteristic, (ii) an interval analysis filter that uses interval analysis to include the relations between the different performances, and (iii) a rule-based filter for possible heuristic modifications to the final ranking.…”