An efficient design environment and algorithms for transport processing FPGA

Abstract

We introduce a CAD system for the original FPGA "PROTEUS", which has several features suitable for the effciernt realization of practical digital transport processing systems. These features are considered in the design of the CAD system. Our CAD system supports both automatic and manual design environments. The automatic design environment offers complete top-down design from high-level hardware description to dovvnloading the programming data into the FPGA. In the manual design environment, an interactive chip editor is provided that enables high-performance circuits to be constructed skillfully. This paper introduces our design strategy and the algorithms that realize them.

A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

“…The proposed algorithm has been implemented on SUN Sparc Station 2 (28.5 MIPS) in C language and experimented on PROTEUS, a transport-processing FPGA chip [4], [8], [9]. Table I summarizes puts, LUTs, and latches (#inputs, #outputs, #LUTs, and #FFs, respectively) of transport-processing circuits to be experimented.…”

“…Table I summarizes puts, LUTs, and latches (#inputs, #outputs, #LUTs, and #FFs, respectively) of transport-processing circuits to be experimented. To obtain the circuits except for mpa-tyl and mpa-ty2, we executed a logic synthesizer called PARTHENON [3],1° for behavioral descriptions (SFL files) followed by a technology mapper called procover in PROTEUS-CAD [8]. Primary inputs and outputs are assigned to 1/0 blocks on the left and right side of the chip, respectively, except for mpa-ty2.…”

“…1 based on an FPGA chip proposed in [4], [8], [9]. The model has a two-dimensional array of basic cells.…”

“…As application-specific field-programmable gate arrays (FPGAs), transport-processing FPGAs have been proposed [4], [8], [9].1 In contrast with conventional FPGAs as in [lo], transport-processing FPGAs have finer granularity of logic functions so that they implement more flexible circuits on them. Since transport data processing has strong direction of signal flows, input terminals ~ FPGAs called PROTEIJS have been developed for transport processing [4] ,[SI, [Y].…”

“…Several layout synthesis algorithms have been proposed for transport-processing FPGAs [6], [8]. In [8], partitioning-based placement and maze routing for minimizing critical path delays are proposed. Those algorithms are, however, difficult to generate layouts with small routing congestion and thus do not satisfy the requirement (1).…”