2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) 2016
DOI: 10.1109/inis.2016.070
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An Efficient Design Methodology for CNFET Based Ternary Logic Circuits

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Cited by 11 publications
(6 citation statements)
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“…Based on the abovementioned techniques, different other logic gates such as NAD, NOR, XOR can be constructed. Besides these, several other complex arithmetic circuits like the adder, multipliers, and so on, are also proposed in References [18,[78][79][80][81][82].…”
Section: Carbon Nano Tube Field Effect Transistor-based Ternary Logicmentioning
confidence: 99%
“…Based on the abovementioned techniques, different other logic gates such as NAD, NOR, XOR can be constructed. Besides these, several other complex arithmetic circuits like the adder, multipliers, and so on, are also proposed in References [18,[78][79][80][81][82].…”
Section: Carbon Nano Tube Field Effect Transistor-based Ternary Logicmentioning
confidence: 99%
“…It shows clearly that in terms of PDP, the proposed GNRFET based ternary half-adder offers a significant improvement over other designs. There are a few designs available, which can significantly decrease the transistor count [38], [39]. These papers focus on the transistor-level designs of half-adder circuits.…”
Section: E Ternary Multiplexermentioning
confidence: 99%
“…The literature contains various ternary logic circuits designed using CNTFETs. Ternary circuits like the basic logic gates, adders, multipliers, and ALU are designed and implemented in the existing research papers [5]- [29]. A few recent research papers [30] [31] present the idea of a ternary logic processor, but a complete design of a ternary logic processor at the transistor level is not presented in the literature yet.…”
Section: Introductionmentioning
confidence: 99%