An efficient design of edge-triggered synchronous memory element using quantum dot cellular automata with optimized energy dissipation

Patidar, Mukesh; Gupta, Namit

doi:10.1007/s10825-020-01457-x

Cited by 28 publications

(7 citation statements)

References 33 publications

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“…7 [13]. The signal flow in any QCA circuits controlled by Landauer clocks which has four different phases first-Switch, second-Hold, third-Release and fourth-Relax [21][22][23][24][25][26][27][28][29][30]. The phases of wires are calculated by Eq.…”

Section: Fundamental Of Qca-design Technologymentioning

confidence: 99%

WITHDRAWN: Optimal energy estimation of Toffoli and Peres gate design using quantum-dot cellular automata

Patidar¹,

Gupta²

2021

Preprint

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Quantum-dot cellular automata (QCA) are a novel dominant transistor-less computational nanotechnology. It is an appropriate candidate for the upcoming generation of quantum computational nano-electronics technology. The main objective of this research work is to present a QCA reversible logic circuits design such as the Toffoli gate (TG) and Peres gate (PG) and do the analysis of different parameters. In this paper, we propose a single layer coplanar method to solve this physical layout design and synchronization problem. The presented reversible logic gate (RLG) layout designs are implemented by Bijection functional algorithm for reduction of the number of QCA (quantum) cells, latency, and minimum design area. Also, the Optimized energy dissipation and effect of temperature on output polarization cell, of the proposed structure have been checked successfully using the tool QD-E (Energy) tool. The proposed QCA design has been verified by QCADesigner-E 2.2 tool using a bistable approximation and coherence vector engine. Finally, comparisons have been proposed RLG-TG and RLG-PG designs with the existing QCA design.

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Section: Fundamental Of Qca-design Technologymentioning

confidence: 99%

WITHDRAWN: Optimal energy estimation of Toffoli and Peres gate design using quantum-dot cellular automata

Patidar¹,

Gupta²

2021

Preprint

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“…A graphical representation of the area-latency-cost-comparison based on the given table 5 is also shown over here in figure 12. That above structure proves that, the proposed 4-bit 3-layered adder circuitry with ripple-borrow-out not only reduce the occupied area, delay and cell-complexity, but also reduce the area-utilization-factor (AUF) [22] and cost of the design, which depends on area and latency or delay of the design, with 1.2 nW areal power-dissipation [23]. The equation of area-utilization-factor is also given below as eq.…”

Section: Results Of Proposed Multi-bit Structurementioning

confidence: 67%

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

Sarkar¹

2021

pae

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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.

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“…QCADesigner‐E 57–59 is used to calculate the energy of developed shift register circuits. The rate and change of tunnelling energy, as well as the clock cycle, affect circuit power consumption 59 . In addition, it is contingent on the number of majority gates 59 .…”

Section: Energy Calculations Of the Proposed Circuitsmentioning

confidence: 99%

“…The rate and change of tunnelling energy, as well as the clock cycle, affect circuit power consumption 59 . In addition, it is contingent on the number of majority gates 59 . Moreover, E_bath_total, E_Error_total, Sum_bath, and Avg_bath signify the sum of energy transferred to the bath, the summation of each cell's error for each clock, total energy dissipation, and per clock cycle, respectively 57–59 …”

Section: Energy Calculations Of the Proposed Circuitsmentioning

confidence: 99%

“…59 In addition, it is contingent on the number of majority gates. 59 Moreover, E_bath_total, E_Error_total, Sum_bath, and Avg_bath signify the sum of energy transferred to the bath, the summation of each cell's error for each clock, total energy dissipation, and per clock cycle, respectively. [57][58][59] The various energy parameters and measurement values of the shift register design shown in Figure 17 and the obtained energy in different shift register modes at different temperatures is calculated and shown in Figures 18,19 Based on the obtained results that are shown in Table 6 and Figure 18, the proposed 1-and 3-layer 3-bit shift register circuits have the high energy consumption with appropriate thermal stability in temperature 1 K and suitable energy consumption with appropriate thermal stability in 5 K. In addition, based on the obtained results that are shown in Table 7 and Figure 19, the proposed 1-and 3-layer 4-bit shift register circuits have the high energy consumption with appropriate thermal stability in temperature 1 K and suitable energy consumption with appropriate thermal stability in 5 K. Moreover, based on the obtained results that are shown in Table 8 and Figure 20, the proposed 1-, and 5-layer, 5-bit shift register circuits have the suitable energy consumption with appropriate thermal stability in temperatures 1 K and 15 K.…”

Section: Energy Calculations Of the Proposed Circuitsmentioning

confidence: 99%

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Novel multilayer SISO shift register architecture in QCA technology and its usage in communications

Divshali

Rezai

Karimi

2022

Int J Communication

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Summary The QCA technology is a promising emerging technology at nano‐scale for replacing CMOS technology. Shift register has a vital role in communication networks and digital electronic circuits that are the main components of integrated circuits and memory. In this study, novel and efficient delay circuit (pseudo‐D‐Latch) is designed. Then, 3‐, 4‐, and 5‐bit SISO QCA shift register architectures are developed and evaluated in single layer, 3‐layer and 5‐layer using the designed delay circuit. The designed architectures are evaluated using QCADesigner‐E tool version 2.2. The results demonstrate that the pseudo‐D‐Latch circuit contains 17 cells and 0.01 μm2 area. The 3‐, 4‐, and 5‐bit single layer SISO QCA shift register architecture contains 63 (0.05 μm2), 85 (0.66 μm2), and 107 (0.08 μm2) cells (area), respectively. The 3‐ and 4‐bit 3‐layer SISO QCA shift register architecture contains 63 (0.03 μm2) and 84 (0.03 μm2) cells (area), respectively. The 3‐ and 5‐bit 5‐layer SISO QCA shift register architecture contains 62 (0.02 μm2) and 105 (0.032 μm2) cells (area), respectively. These results show that the designed QCA architectures provide improvements compared with other SISO QCA architectures.

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An efficient design of edge-triggered synchronous memory element using quantum dot cellular automata with optimized energy dissipation

Cited by 28 publications

References 33 publications

WITHDRAWN: Optimal energy estimation of Toffoli and Peres gate design using quantum-dot cellular automata

WITHDRAWN: Optimal energy estimation of Toffoli and Peres gate design using quantum-dot cellular automata

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

Novel multilayer SISO shift register architecture in QCA technology and its usage in communications

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