An efficient design of low-power and high-speed approximate compressor in FinFET technology

Zakian, Pegah; Asli, Rahebeh Niaraki

doi:10.1016/j.compeleceng.2020.106651

Cited by 17 publications

(12 citation statements)

References 19 publications

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“…Both these designs have GC greater than three hundred and QC greater than thousand, which makes them undesirable in reversible logic based realisations. Multipliers MULT-2 [4], MULT-3 [4], MULT-5 [5] and MULT-9 [12] have lower reversible logic realisation parameters, when compared to other inexact compressor based multiplier designs, However, the ER in these compressors employed are greater than 31%, which is not desirable. The proposed design is able to achieve low GC as the above mentioned designs with a QC of 852.…”

Section: A Experimental Analysis Of Proposed Compressor Designmentioning

confidence: 98%

“…The analysis is carried out for the existing and proposed inexact 4 : 2 compressor based multiplier architectures for seeded random 32000 input combinations and a comparison of the same is presented in Table 9. MED is the highest for MULT-5 [5], MULT-2 [4], MULT-9 [12] and MULT-4 [8] due to high ER in the compressors used. Low MED is for MULT-11, MULT-6 [6], MULT-10 [9] and MULT-7 [7] as the ER in these design are low.…”

Section: A Experimental Analysis Of Proposed Compressor Designmentioning

confidence: 99%

“…MRED is the highest for MULT-5 [5] and is 0.1144. MULT-2 [4], MULT-9 [12] and MULT-8 [10] also have high MRED which is not desirable for multiplier implementation. Low MRED is seen in MULT-11, MULT-6 [6], MULT-10 [9] and MULT-7 [7].…”

Section: A Experimental Analysis Of Proposed Compressor Designmentioning

confidence: 99%

“…In the recent times, multipliers are explored in the light of approximation as they find huge demand in realising area and power optimised design for error tolerant applications like multimedia processing, neural network, signal processing, etc. Recently, such optimisations in CMOS [4]- [9], FPGA [10], pass transistor [11] and FinFET [12] based multiplier realisations are being researched.…”

Section: Introductionmentioning

confidence: 99%

“…Chang et al [11] have proposed approximate 4 : 2 compressor optimised for pass transistor based implementation. FinFET based implementation for approximate 4 : 2 compressor was proposed by Zakian et al [12].…”

Section: Introductionmentioning

confidence: 99%

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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

et al. 2021

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This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4 : 2 compressor optimised for realisation using reversible logic. The proposed inexact 4 : 2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the proposed reversible logic based realisation of the proposed inexact 4 : 2 compressor and Baugh-Wooley Wallace tree multiplier is measured in scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) and Ancilla Input (AI). The proposed inexact 4 : 2 compressor is able to reduce reversible logic realisation metrics GC, QC, GO and AI by 50%, 15%, 25% and 11.11% as compared to reversible logic realisation of exact 4 : 2 compressor. An 8 × 8 Baugh-Wooley Wallace tree multiplier is implemented in this paper and is utilised in two applications 1) image processing -one level decomposition using rationalised db6 wavelet filter bank and image smoothing and 2) Convolutional Neural Networks (CNN). The efficacy of the proposed multiplier in image processing applications is estimated by measuring Structural Similarity Index Measure (SSIM) which is found to be 0.96 and 0.84 for image decomposition and smoothing respectively. In CNN based application, the efficiency is measured in scales of accuracy and is found to be 97.1%.

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Section: A Experimental Analysis Of Proposed Compressor Designmentioning

confidence: 98%

Section: A Experimental Analysis Of Proposed Compressor Designmentioning

confidence: 99%

Section: A Experimental Analysis Of Proposed Compressor Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

et al. 2021

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An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

Odugu

C²,

2021

Circuit Theory & Apps

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The very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

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Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

Das

Maity

Chowdhury

et al. 2021

Int J RF Mic Comp-Aid Eng

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This dissertation demonstrates the reliability issues associated with the temperature of Ge multi‐channel fin shaped field‐effect transistor (Mch‐FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub‐threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch‐FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut‐off frequency, and intrinsic gain with lowering of temperature. However, Mch‐FinFET device provides a significant improvement of higher‐order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch‐FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

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An efficient design of low-power and high-speed approximate compressor in FinFET technology

Cited by 17 publications

References 19 publications

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

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