High speed multimedia applications have paved way for a whole new area in high speed error-tolerant circuits with approximate computing. These applications deliver high performance at the cost of reduction in accuracy. Furthermore, such implementations reduce the complexity of the system architecture, delay and power consumption. This paper explores and proposes the design and analysis of two approximate compressors with reduced area, delay and power with comparable accuracy when compared with the existing architectures. The proposed designs are implemented using 45 nm CMOS technology and efficiency of the proposed designs have been extensively verified and projected on scales of area, delay, power, Power Delay Product (PDP), Error Rate (ER), Error Distance (ED), and Accurate Output Count (AOC). The proposed approximate 4 : 2 compressor shows 56.80% reduction in area, 57.20% reduction in power, and 73.30% reduction in delay compared to an accurate 4 : 2 compressor. The proposed compressors are utilised to implement 8 × 8 and 16 × 16 Dadda multipliers. These multipliers have comparable accuracy when compared with state-of-the-art approximate multipliers. The analysis is further extended to project the application of the proposed design in error resilient applications like image smoothing and multiplication.

This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4 : 2 compressor optimised for realisation using reversible logic. The proposed inexact 4 : 2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the proposed reversible logic based realisation of the proposed inexact 4 : 2 compressor and Baugh-Wooley Wallace tree multiplier is measured in scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) and Ancilla Input (AI). The proposed inexact 4 : 2 compressor is able to reduce reversible logic realisation metrics GC, QC, GO and AI by 50%, 15%, 25% and 11.11% as compared to reversible logic realisation of exact 4 : 2 compressor. An 8 × 8 Baugh-Wooley Wallace tree multiplier is implemented in this paper and is utilised in two applications 1) image processing -one level decomposition using rationalised db6 wavelet filter bank and image smoothing and 2) Convolutional Neural Networks (CNN). The efficacy of the proposed multiplier in image processing applications is estimated by measuring Structural Similarity Index Measure (SSIM) which is found to be 0.96 and 0.84 for image decomposition and smoothing respectively. In CNN based application, the efficiency is measured in scales of accuracy and is found to be 97.1%.

Haar Wavelet transform is an efficacious class of wavelet transform that satisfies both symmetry and orthogonality properties which are crucial in handling boundary distortion and energy preservation in image processing applications. Such applications demand power efficient design solutions that deliver high performance. Reversible logic has emerged as a solution that incorporates logical and physical reversibility to realise low power designs. This paper presents a reversible logic based design of Haar wavelet transform and lifting scheme for Haar wavelet transform, a first in literature of reversible logic. The designs are analysed to measure the efficiency of reversible logic implementations in terms of Quantum Cost (QC), Constant Inputs (CI), Garbage Outputs (GO) and Gate Count (GC). Furthermore, this paper proposes two architectures for Reversible Approximate Full Adder (RAFA)-RAFA-1 and RAFA-2; optimised explicitly for reversible logic based implementation. The proposed architectures have 25% Error Rate (ER) and optimised QC, CI, GC and GO when compared to existing exact and approximate full adder architectures implemented using reversible logic. Functional verification of the proposed architectures are performed on FPGA using 512 × 512 image. The efficiency of the image processing application is projected in terms of Structural Similarity Index Measure (SSIM) and Peak Signal to Noise Ratio (PSNR). Average SSIM and average PSNR are found to be 0.9679 and 31.81dB for RAFA-1 and 0.9696 and 32.15dB for RAFA-2 which are comparable with exact full adder based design.

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This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image with a filter kernel. This work proposes reversible logic based design and implementation of six filter kernels. The filter kernels implemented are Gaussian blur, Laplacian outline, Sobel, Emboss, Sharpen and Prewitt edge detection. The kernels are implemented individually using reversible logic gates and the designs are measured in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The functional verification is carried out using 512 × 512 standard images on Kintex 7 FPGA platform. The filtered images from the proposed design have an average structural similarity index of 0.92. 12 IET Image Process.