FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics

Barve, Sampada; Raveendran, Sithara; Korde, Charudatta; Panigrahi, Trilochan; Kumar, Yogesh; Vasantha, M. H.

doi:10.1109/ises.2018.00012

Cited by 7 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These systems heavily rely on adders, multipliers, and squarers [21][22][23]. The current multipliers and squarers (precisely their related adders), which form the central part of these systems, affect their speed and area [18]. The more complex squarers and multipliers or their related adders are, the more they influence the rate and size [2,24].…”

Section: Methodsmentioning

confidence: 99%

“…The implementation of this squarer involved comparators, adders subtractors, shifters, and other components, and it was improved by about 27% in terms of speed. Additionally, authors in [18] presented two designs for squaring circuits of size 8-bit and 16 -bit, respectively. The first one is based on Antyayordashakepi Sutra, while the other uses the Duplex method.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

View full text Add to dashboard Cite

Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

View full text Add to dashboard Cite

show abstract

Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

Ananthalakshmi,

Divyaparameswari,

Kanimozhi

2023

Machine Learning for VLSI Chip Design

View full text Add to dashboard Cite

High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA

Sujitha

Kailath

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryHardware implementation of dedicated arithmetic modules is inevitable for any signal processing system development and computational complexity of such modules could be significantly reduced with improved performance by utilizing Vedic algorithms. Five novel Vedic arithmetic modules for multiplication, square, cube, square root, and cube root are implemented on Zedboard Zynq‐7000 FPGA. A novel 4:2 compressor that uses only primitive gates in critical path is proposed to reduce partial products in the Urdhwa Tiryakhbhyam parallel multiplier achieving the best performance reported so far. Elimination of recursiveness in Antyayordashekepi‐Dwanda squarer results in reduced area while modified Dwanda squarer results in reduced delay. Anurupyena cubic module with 4:2 and 5:2 compressors is implemented from which the one with 4:2 compressor provides the least delay with more than 50% reduction with respect to that of reported cube modules. Modified Vargamula square root and modified cube root modules are also implemented incorporating pipelining, priority encoder, and padding of zero's to achieve better performance. In addition to the delay, in terms of area occupancy, power, and energy consumed (power‐delay‐product), better or comparable performance is also achieved by all the above‐mentioned modules implemented. The dedicated multiplier is used in a 64‐point FFT Implementation and results similar to existing structures are obtained.

show abstract

FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics

Cited by 7 publications

References 11 publications

Vedic-Based Squarers with High Performance

Vedic-Based Squarers with High Performance

Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA

Contact Info

Product

Resources

About