Haar Wavelet transform is an efficacious class of wavelet transform that satisfies both symmetry and orthogonality properties which are crucial in handling boundary distortion and energy preservation in image processing applications. Such applications demand power efficient design solutions that deliver high performance. Reversible logic has emerged as a solution that incorporates logical and physical reversibility to realise low power designs. This paper presents a reversible logic based design of Haar wavelet transform and lifting scheme for Haar wavelet transform, a first in literature of reversible logic. The designs are analysed to measure the efficiency of reversible logic implementations in terms of Quantum Cost (QC), Constant Inputs (CI), Garbage Outputs (GO) and Gate Count (GC). Furthermore, this paper proposes two architectures for Reversible Approximate Full Adder (RAFA)-RAFA-1 and RAFA-2; optimised explicitly for reversible logic based implementation. The proposed architectures have 25% Error Rate (ER) and optimised QC, CI, GC and GO when compared to existing exact and approximate full adder architectures implemented using reversible logic. Functional verification of the proposed architectures are performed on FPGA using 512 × 512 image. The efficiency of the image processing application is projected in terms of Structural Similarity Index Measure (SSIM) and Peak Signal to Noise Ratio (PSNR). Average SSIM and average PSNR are found to be 0.9679 and 31.81dB for RAFA-1 and 0.9696 and 32.15dB for RAFA-2 which are comparable with exact full adder based design.

This paper presents a two-path design of quadrature band-pass ΣΔ modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch is analyzed and a twopath quadrature cascaded modulator is proposed to alleviate signal band gain error tone. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.