An efficient designed prototype technique for OFDM PAPR reduction using FPGA

Abstract

In this paper, a proposed designed technique to reduce Orthogonal Frequency Division Multiplexing (OFDM) Peak-to-Average Power Ratio (PAPR) value is done. This designed technique contains new block which is inserted in the OFDM system. This proposed block is applied to WiMAX system as an example of OFDM technology. Afterwards, several MATLAB programs are executed to discuss the behavior and the characteristics of this proposed block. In addition, the effect of its insertion on the original system is studied. Due to this insertion, 0 dB OFDM PAPR value can be achieved. Furthermore, it can be synthesized practically. This proposed system is implemented over Field Programmable Gate Array (FPGA). The designed circuit is characterized by both its low complexity and its high speed. Moreover, it is portable circuit. This means that it can be implemented over any FPGA kit regardless of its technology.

Low complexity Wizard amplitude shaping system for peak‐to‐average power ratio reduction

“…Obviously, the proposed WAS system has better results than the conventional OFDM system for N Z = 0 and N Z = 1 by 7 and 1 dB at 10 −2 BER, respectively. It is worth mentioned the best case of BER performance gain with the previous constant envelope OFDM system [7] is 2 dB gain, while with the constant amplitude OFDM [5] is about 6.6 dB. Therefore the proposed WAS system is superior to [7] when N Z = 0 is chosen. For ITU Pedestrian‐A multipath fading channel: The BER plots for the two proposed systems with the N Z change, are shown in Fig.…”

“…Noteworthy, the complexity of our two proposed techniques are very low compared to the previous constant envelope technique in [7] which requires oversampling, integrator and grossly look‐up tables, a band‐pass filter, two complex multipliers, two low‐pass filters, arc‐tan function generator, phase unwrapper, matched filters and hard decisions. Also, the two proposed techniques have a hardware complexity close to [5].…”

“…In addition, other techniques close to our proposed technique are suggested, such as in [5], a proposed technique is explained to convert the OFDM signal into a square wave which reduce the PAPR value to 0 dB. Also, the hardware implementation is executed for the proposed system.…”

“…Unfortunately, the hardware complexity of this technique is very large. In addition, a small system performance enhancement is introduced compared to [5].…”

The implementation of the clustered‐OFDM‐based transceiver on an FPGA device: A comprehensive comparison

“…The use of FPGA platforms to accommodate the OFDM transmitters of both IEEE 802.11a and 802.16-2004 standards was addressed in [49,50]. The implementation of individual parts of OFDM transceivers, such as FFT and its inverse [51,52], a peakto-average power ratio (PAPR) reduction [53], an interleaving [54], a higher-order square M Quadrature amplitude modulation (QAM) detection/demodulation [19], a 64-QAM demodulator [55], a channel error detection and correction [56], and baseband transmitter [57,58] have been investigated so far. Overall, these contributions show the suitability, flexibility, and abundance of resources of FPGA platforms, such as lookup table (LUT), memory, multipliers, and other intellectual property (IP) for designing high-speed and reconfigurable transceivers.…”