An Efficient Hardware LDPC Encoder Based on Partial Parallel Structure for CCSDS

Wang, Zhaohui; Hao, Xin; Lin, Changxing; Wu, Qiuyu

doi:10.1109/icct.2018.8599970

Cited by 6 publications

(4 citation statements)

References 14 publications

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“…Table II also shows the comparison with existing encoder architectures. Compared with three high-rate 4R4JA LDPC encoder architectures in [9] and [28], especially the most similar (30480, 24384) encoder, the proposed architecture has a 4.8x higher TROR on the same FPGA platform. Meanwhile, compared with four high-rate (8176, 7154) C2 LDPC encoder architectures in [7,9,29,30], only the architecture in [7] has a slightly higher TROR than this letter.…”

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Bao,

Guan,

Liang

et al. 2024

IEICE Electron. Express

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Globally-coupled low-density parity check (GC-LDPC) codes have shown great application potential in the error correction of NAND Flash memories. However, the existing LDPC encoder architectures cannot fully use the structure characteristic of GC-LDPC codes. In this letter, focusing on the particular globally-coupled structure, we propose a memory-efficient multiplex-parallel GC-LDPC encoding method and corresponding efficient GC-LDPC encoder architecture. By reusing the local submatrices and optimizing the operation order of piecewise parity bits, the proposed encoding method has low storage overhead and encoding complexity. Then, based on the designed extended shift-register-adderaccumulator (E-SRAA) unit and barrel shifter, we optimize the operator scheduling of the proposed GC-LDPC encoding method when its local encoding is different. The implementation results under various FPGA technologies show that the proposed GC-LDPC encoder architecture achieves a markedly higher throughput-to-resource overhead ratio than existing similar LDPC encoder architectures. Meanwhile, it can meet the bandwidth requirement of ONFI 6.0.

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Section: Implementation Results and Comparisonsmentioning

confidence: 99%

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Bao,

Guan,

Liang

et al. 2024

IEICE Electron. Express

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show abstract

“…Previous works in [26,27,28,29,30] target CCSDS codes. A variety of encoding circuits based on shift registers have been proposed in [26].…”

Section: Introductionmentioning

confidence: 99%

“…The encoding complexity of these encoding circuits is linearly proportional to the number of parity check bits of the code, or the total bits of the code in case of a parallel approach. In [27], the proposed partial parallel encoder architecture involves wide XOR operations over a significant number of bits and requires much register resources for the shift registers. The high throughput encoder described in [28] exploits the parallel recursive convolutional encoder circuit structure to reduce the use of system registers at the cost of a four fold increase in the multiplication and accumulation units.…”

Section: Introductionmentioning

confidence: 99%

Low-complexity encoder implementation for LDPC codes in CCSDS standard

Chen

Han

2021

IEICE Electron. Express

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The traditional direct LDPC encoder in CCSDS standard for space application needs to store the first row in each submatrix of the generator matrix, making the circuit implementation complex. To solve this problem, a low-complexity encoder for LDPC codes is implemented in this letter. The encoder stores the vector in random-access memory (RAM). To implement the multiplication of sparse matrix and vector with limited hardware resources, the encoder takes the row indexes of nonzero entries in each column of sparse matrix as the write address of the RAM. Moreover, the shift-register-adder-accumulator is exploited to implement the multiplication of the dense core matrix and the vector, greatly reducing the storage and computation complexity. The LDPC encoder with the code rate of 1/2 in the CCSDS standard is implemented on Xilinx XC6VLX240T FPGA chip, and the implementation results indicate that the proposed encoder consumes 50% less hardware resources than the traditional direct encoder.

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“…With the continuous development of LDPC codes, these codes have been gradually used in deep space communication. CCSDS has been working on the standardization of LDPC codes and recommended a class of LDPC codes suitable for deep space applications [8]- [10].…”

Section: Introductionmentioning

confidence: 99%

Research of LT Code Based on Key Information Feedback in Deep Space Communication

et al. 2020

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CCSDS LDPC code cannot effectively solve the problems of communication interruptions and high communication error rates in deep space communication. An application scheme of digital fountain code for deep space communication is thoroughly studied in this paper. First, an improved joint coding and decoding algorithm for LT code is proposed by adjusting the probability of the source symbol selection to achieve a nonuniform selection coding algorithm and by introducing the idea of real-time decoding on the basis of combining the BP and GE decoding algorithms to disperse the decoding complexity. Second, to ensure that the LT code can be reliably transmitted under different channel conditions, a feedback information extraction method and a retransmission coding method are designed, and an LT code transmission scheme based on key information feedback is proposed. Finally, the concatenation of the LDPC code with the LT code based on key information feedback is proposed. The LDPC code processing can be equivalently run on deep-space channels as erasure channels so that the advantage of the LT code being rateless can still be exploited in deep-space communication. Through simulation experiments, the performance of the cascade codes is analyzed from the two aspects of decoding efficiency and decoding overhead, and the performance of the cascade codes and CCSDS LDPC codes are compared from the perspective of the bit error rate. Simulation results show that the decoding efficiency of the cascade code increases, the decoding overhead decreases, and the communication bit error rate is lower in deep space communication compared with the CCSDS LDPC code. Therefore, the cascade code can improve the reliability of deep space communication.

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An Efficient Hardware LDPC Encoder Based on Partial Parallel Structure for CCSDS

Cited by 6 publications

References 14 publications

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Low-complexity encoder implementation for LDPC codes in CCSDS standard

Research of LT Code Based on Key Information Feedback in Deep Space Communication

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