Low-complexity encoder implementation for LDPC codes in CCSDS standard

Abstract

The traditional direct LDPC encoder in CCSDS standard for space application needs to store the first row in each submatrix of the generator matrix, making the circuit implementation complex. To solve this problem, a low-complexity encoder for LDPC codes is implemented in this letter. The encoder stores the vector in random-access memory (RAM). To implement the multiplication of sparse matrix and vector with limited hardware resources, the encoder takes the row indexes of nonzero entries in each column of sparse matrix as the write address of the RAM. Moreover, the shift-register-adder-accumulator is exploited to implement the multiplication of the dense core matrix and the vector, greatly reducing the storage and computation complexity. The LDPC encoder with the code rate of 1/2 in the CCSDS standard is implemented on Xilinx XC6VLX240T FPGA chip, and the implementation results indicate that the proposed encoder consumes 50% less hardware resources than the traditional direct encoder.

Security-based low-density parity check encoder for 5G communication

“…One of the primary channel-coding techniques used in 5G is referred to as "LDPC codes". The creation of safe channel coding techniques is one of the most crucial defense strategies for 5G technology's  ISSN: 2302-9285 channel coding against side-channel attacks [19]. The multiplicative masking technique is used in the current study for LDPC codes to increase network security for 5G systems.…”

Low-Latency QC-LDPC Encoder Design for 5G NR

“…The design can be easily reconstructed to support variable code rates and code lengths through parameter configuration. In [13], the encoder stores the matrix vector in random access memory (RAM). The row index of the non-zero entry in each column of the sparse check matrix is used as the write address of the RAM, which reduces the complexity of storage and calculation.…”