An Efficient Heterogeneous Memristive xnor for In-Memory Computing

Lebdeh, Muath Abu; Abunahla, Heba; Mohammad, Baker; Al‐Qutayri, Mahmoud

doi:10.1109/tcsi.2017.2706299

Cited by 40 publications

(16 citation statements)

References 42 publications

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“…Their technique achieves higher energy efficiency and performance compared to general-purpose processor and DRAM-based PIM techniques. Lebdeh et al [76] presented a design for implementing stateful XNOR/XOR gate in MCA. Their design uses two "bipolar memristors (BMs)" for storing input and one "unipolar memristor (UM)" for storing the output.…”

Section: Arithmetic and Logical Operationsmentioning

confidence: 99%

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A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

Mittal

2018

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130

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As data movement operations and power-budget become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as processing-in-memory (PIM), machine learning (ML), and especially neural network (NN)-based accelerators has grown significantly. Resistive random access memory (ReRAM) is a promising technology for efficiently architecting PIM- and NN-based accelerators due to its capabilities to work as both: High-density/low-energy storage and in-memory computation/search engine. In this paper, we present a survey of techniques for designing ReRAM-based PIM and NN architectures. By classifying the techniques based on key parameters, we underscore their similarities and differences. This paper will be valuable for computer architects, chip designers and researchers in the area of machine learning.

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Section: Arithmetic and Logical Operationsmentioning

confidence: 99%

“…The limitation of their design is that it needs both bipolar and unipolar memristors and uses multiple voltage levels. [76]).…”

Section: Arithmetic and Logical Operationsmentioning

confidence: 99%

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

Mittal

2018

MAKE

130

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“…[ 19 ] Recently, several studies have reported the use of one transistor–one resistor devices (1T1R) as binary XNOR cells to reduce data storage and transfer. [ 19–21 ] In addition, implementation of XNOR gates using two RRAM devices with complementary encoding has been demonstrated. [ 22 ] However, to implement XNOR cell‐based high‐density arrays, it is necessary to execute the XNOR function using a simple structure and two‐terminal‐based 1S1R devices.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Memory Device (Memory/Selector) with Scalable and Simple Structure for XNOR‐Based Neural Network Applications

Sung

Kim

Kwak

et al. 2021

Adv Elect Materials

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This study investigates the electrical behavior of a hybrid memory device with both memory and selector characteristics. Electrical measurements and simulations indicate that the electrical behaviors (nonvolatile characteristics in Al2O3 layers and volatile characteristics in TiO2 layers) are linked to the stability of the conductive filament (CF) used. The binding energy between the Ag atoms in the CF is crucial for achieving nonvolatile or volatile characteristics. Thus, the hybrid memory device exhibits tunable threshold‐voltage characteristics and a consistent off‐state without requiring an additional selector device. Furthermore, the buffer metal layer between the active electrode and oxide layer affects the filament‐formation process in terms of the switching time. Experimental results show that the buffer layer significantly affects ion motion, such as redox reactions and ion migration. Thus, hybrid memory devices with a Zr buffer layer can solve the voltage–time dilemma, enabling fast and low‐voltage switching. Robust XNOR‐based neural network applications are developed using hybrid memory devices in a cross‐point array with characteristics such as scalability, simple structure, and excellent switching characteristics. By carefully considering the on–off ratio and device variability, hybrid memory devices can ensure reliable operation with a high pattern recognition accuracy in XNOR‐based neural neuromorphic hardware systems.

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“…Emerging resistive random-access memory (RRAM) technology such as the memristor (MR), postulated by Chua in 1971 [13], is a two-terminal element that plays a great role in the electronic technology due to its low power consumption, highdensity integration and fast write/read operations [14]. Additionally, the ability of MRs to retain their resistance state makes them suitable for non-volatile RRAM, programmable logic and in-memory computing applications [15,16]. Besides using MRs in two-level memories, MRs can also store multiple bits in a single memory cell to form the multi-level cell (MLC), which leads to dense and power-efficient memories [17][18][19].…”

Section: Introductionmentioning

confidence: 99%

On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

Humood

Mohammad

Abunahla

et al. 2020

IET Circuits, Devices & Systems

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This study presents a novel hybrid memristor (MR)-complementary metal-oxide-semiconductor-based flash analogue-to-digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi-state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage-threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR-based flash-ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post-processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non-linearity and integral non-linearity errors compared with the conventional design.

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An Efficient Heterogeneous Memristive xnor for In-Memory Computing

Cited by 40 publications

References 42 publications

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

Hybrid Memory Device (Memory/Selector) with Scalable and Simple Structure for XNOR‐Based Neural Network Applications

On‐chip tunable Memristor‐based flash‐ADC converter for artificial intelligence applications

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