An efficient interpolation filter VLSI architecture for HEVC standard

Abstract

The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

“…The experimental results demonstrate that this approach have speed up the run time by around 2 times compared to a software implementation of HEVC on CPU (Central Processing Unit) with a modest increase of bitrate (0.51%), a too negligible decrease in PSNR (0.01%) although the complexity present in the HEVC standard. In comparison with other reported results in in the literature, this present work can reach a higher accelerated encoding time (40%) compared to previous works 3,5 that present only 28% and 19.7%, respectively, in the gain of encoding time. The software implementation of HEVC 3 presents higher increase in bitrate (4.07%) compared to the proposed HW/SW HEVC implementation that presents only 0.51%.…”

“…In terms of hardware resources, the amount of logic resources (2801) is too reduced compared to the work reported in reference Ghani et al 7 that takes 4426 to implement both luma and chroma filters for both directions (horizontal and vertical). On the other hand, Zhou et al 5 consume a higher amount of logic resources (37.2k) to implement just the luma filters, which can be explained by the high video resolution implemented (8k ultrahigh definition [UHD] equivalent to 7680 × 4320 pixels). The power consumption (3.308 mW) is optimized too (compared with results reported in Zhou et al 5 ).…”

“…On the other hand, Zhou et al 5 consume a higher amount of logic resources (37.2k) to implement just the luma filters, which can be explained by the high video resolution implemented (8k ultrahigh definition [UHD] equivalent to 7680 × 4320 pixels). The power consumption (3.308 mW) is optimized too (compared with results reported in Zhou et al 5 ). Also, this proposed design can support resolutions higher than full HD (2560 × 1600) compared to what reported by Zhou et al 5 that supports only 1280 × 720.…”

“…The power consumption (3.308 mW) is optimized too (compared with results reported in Zhou et al 5 ). Also, this proposed design can support resolutions higher than full HD (2560 × 1600) compared to what reported by Zhou et al 5 that supports only 1280 × 720.…”

“…As a result, the implemented design uses 52.9% less logic elements with a 0.9% increase in bit rate. Another interpolation architecture was proposed by Zhou et al; 5 based on the analysis results of a previously proposed architecture of the FME block, a pipeline reconfigurable interpolation filter design for both half and quarter pixels is proposed too where the 16 × 16 and 64 × 64 blocks are interpolated using 8 × 8 block. This proposed design can save to 19.7% processing time on average with acceptable coding quality degradation (0.12%).…”