An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCL

Pu, Yuliang; Peng, Jun; Huang, Letian; Chen, John

doi:10.1109/fccm.2015.7

Cited by 58 publications

(28 citation statements)

References 5 publications

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“…Normal data are filtered at the NIC and only anomaly data are transferred to the host machine to reduce data size. In addition, KNN (K-Nearest Neighbor) algorithm is accelerated by using FPGAs in papers [13], [14]. It can be used for outlier detection on timeseries data.…”

Section: Related Workmentioning

confidence: 99%

An FPGA-Based Change-Point Detection for 10Gbps Packet Stream

Iwata

Nakamura

Tokusashi

et al. 2019

IEICE Trans. Inf. & Syst.

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In statistical analysis and data mining, change-point detection that identifies the change-points which are times when the probability distribution of time series changes has been used for various purposes, such as anomaly detections on network traffic and transaction data. However, computation cost of a conventional AR (Auto-Regression) model based approach is too high and infeasible for online. In this paper, an AR model based online change-point detection algorithm, called Change-Finder, is implemented on an FPGA (Field Programmable Gate Array) based NIC (Network Interface Card). The proposed system computes the change-point score from time series data received from 10GbE (10Gbit Ethernet). More specifically, it computes the change-point score at the 10GbE NIC in advance of host applications. It can find change-points on single or multiple streams using a context memory. This paper aims to reduce the host workload and improve change-point detection performance by offloading ChangeFinder algorithm from host to the NIC. As evaluations, change-point detection in the FPGA NIC is compared with a baseline software implementation and those enhanced by two network optimization techniques using DPDK and Netfilter in terms of throughput. The result demonstrates 16.8x improvement in change-point detection throughput compared to the baseline software implementation. It is corresponding to the 10GbE line rate. Performance and area overheads when supporting multiple streams are also evaluated. key words: Change-point detection, FPGA NIC, 10GbE * This paper is an extended version of our workshop paper [5], by supporting change-point detections on multiple streams.

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Section: Related Workmentioning

confidence: 99%

An FPGA-Based Change-Point Detection for 10Gbps Packet Stream

Iwata

Nakamura

Tokusashi

et al. 2019

IEICE Trans. Inf. & Syst.

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“…The employment of the k ‐NN algorithm was done bearing in mind that it is a highly parallelizable algorithm suitable for hardware implementation and, therefore, eligible for space missions. In fact Pu et al . have implemented a variant of k ‐NN on an ALTERA FPGA device not far from what ESA is developing at the moment.…”

Section: Efficient Labeling and Outlier Detection Through Classificationmentioning

confidence: 99%

“…In fact Pu et al 87 have implemented a variant of k-NN on an ALTERA FPGA device not far from what ESA is developing at the moment. By using the k-NN we prove two points: (a) the classifier must provide as few as possible false positive detections with no requirement to reach to perfect classification rates and (b) the amount of data that need to be transferred to a rover, that is, the PCA coefficients and a reduced labeled data matrix in the case of k-NN is minimum.…”

Section: K-nn Classifiermentioning

confidence: 99%

Introducing a globally consistent orbital‐based localization system

Boukas

Γαστεράτος

Visentin³

2017

Journal of Field Robotics

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In spite of the good performance of space exploratory missions, open issues still await to be solved. In autonomous or composite semi‐autonomous exploration of planetary land surfaces, rover localization is such an issue. The rovers of these missions (e.g., the MER and MSL) navigate relatively to their landing spot, ignoring their exact position on the coordinate system defined for the celestial body they explore. However, future advanced missions, like the Mars Sample Return, will require the localization of rovers on a global frame rather than the arbitrarily defined landing frame. In this paper we attempt to retrieve the absolute rover's location by identifying matching Regions of Interest (ROIs) between orbital and land images. In particular, we propose a system comprising two parts, an offline and an onboard one, which functions as follows: in advance of the mission a Global ROI Network (GN) is built offline by investigating the satellite images near the predicted touchdown ellipse, while during the mission a Local ROI Network (LN) is constructed counting on the images acquired by the vision system of the rover along its traverse. The last procedure relies on the accurate VO‐based relative rover localization. The LN is then paired with the GN through a modified 2D DARCES algorithm. The system has been assessed on real data collected by the ESA at the Atacama desert. The results demonstrate the system's potential to perform absolute localization, on condition that the area includes discriminative ROIs. The main contribution of this work is the enablement of global localization performed on contemporary rovers without requiring any additional hardware, such as long range LIDARs.

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“…An accelerated kNN algorithm implemented on an FPGAbased heterogeneous computing system was presented in [11]. Altera's OpenCL compiler was used for compiling the OpenCL code onto the FPGA.…”

Section: B Overview Of Openclmentioning

confidence: 99%

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Muslim

Demian²,

et al. 2016

Annals of Computer Science and Information Systems

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Abstract-ModernSoCs are getting increasingly heterogeneous with a combination of multi-core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High-level Synthesis (HLS) simplifies FPGA programming by allowing designers to program FPGAs in several high-level languages e.g. C/C++, OpenCL and SystemC.This work focuses on using an HLS based methodology to implement a widely used classification algorithm i.e. k-nearest neighbor on an FPGA based platform directly from its OpenCL code. Multiple fairly different implementations of the algorithm are considered and their performance on FPGA and GPU is compared. It is concluded that the FPGA generally proves to be more power efficient as compared to the GPU. Furthermore, using an FPGA-specific OpenCL coding style and providing appropriate HLS directives can yield an FPGA implementation comparable to a GPU also in terms of execution time.

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An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCL

Cited by 58 publications

References 5 publications

An FPGA-Based Change-Point Detection for 10Gbps Packet Stream

An FPGA-Based Change-Point Detection for 10Gbps Packet Stream

Introducing a globally consistent orbital‐based localization system

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

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