An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Sutter, Bjorn De; Allam, Osman; Raghavan, Praveen; Vandebriel, Roeland; Cappelle, Hans; Aa, Tom Vander; Mei, Bingfeng

doi:10.1007/s11265-009-0412-x

Cited by 7 publications

(2 citation statements)

References 37 publications

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“…Different memory hierarchies can be constructed by using the ADRES core. For example, two levels of data caches can be attached to ADRES [15], or a multiported scratch pad memory can be attached [20], [21]. There is no array of data memories in the ADRES core.…”

Section: B Advantages Of Execution Triggered Computation Modelmentioning

confidence: 99%

BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

Atak

Atalar

2013

IEEE Trans. VLSI Syst.

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We present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable architecture (CGRA) employing an execution-triggering mechanism. A control data flow graph language is presented for mapping the applications to BilRC. The flexibility of the architecture and the computation model are validated by mapping several real-world applications. The same language is also used to map applications to a 90-nm field-programmable gate array (FPGA), giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90-nm technology, and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial very long instruction word digital signal processor processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications. Index Terms-Coarse-grained reconfigurable architectures (CGRA), discrete cosine transform (DCT), fast Fourier transform (FFT), reconfigurable computing, turbo decoder, Viterbi decoder. I. INTRODUCTION T O COMPLY with the performance requirements of emerging applications and evolving communication standards, various architecture alternatives are available. Field-programmable gate arrays (FPGAs) lack run-time programmability, but they compete with their large number of logic resources. To maximize the device utilization, FPGA designers partition the available resources among several sub-applications in such a manner that each application works at the chosen clock frequency and complies with the throughput requirement. The design phases of FPGAs and application-specific integrated circuits (ASICs) are quite similar except that ASICs lack post-silicon flexibility. Unable to exploit the space dimension, digital signal processors (DSPs) fail to provide the performance requirement of many applications due to the limited parallelism that a sequential architecture can provide. This limitation is not due to the Manuscript

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Section: B Advantages Of Execution Triggered Computation Modelmentioning

confidence: 99%

BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

Atak

Atalar

2013

IEEE Trans. VLSI Syst.

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“…The operation between RCA and local memory can be abstracted as all the RCs accessing the local memory initiatively with blocking loads regardless of the various memory architectures. For example, the ADRES adopted a power-efficient, signal-ported, interleaved scratch-pad memory organization [21]. Whereas, the RSPA used multi-bank local memory architecture, in which each bank may be accessed only by the processing elements in the corresponding row.…”

Section: Base Architecturementioning

confidence: 99%

A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYThe Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.

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Coarse-Grained Reconfigurable Array Architectures

Sutter¹,

Raghavan²,

Lambrechts³

2013

Handbook of Signal Processing Systems

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Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

Cited by 7 publications

References 37 publications

BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures

Coarse-Grained Reconfigurable Array Architectures

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