An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms

Xue, Yuankun; Qian, Zhiliang; Wei, Guopeng; Bogdan, Paul; Tsui, Chi-Ying; Mărculescu, Radu

doi:10.1109/nocs.2014.7008757

Cited by 23 publications

(13 citation statements)

References 11 publications

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“…From Figure 8, the proposed platform shows good scalability in terms of reducing the runtime under different network sizes by 10%-90%, 10%-93%, 10%-96% for 3 benchmarks. The improvement of runtime for XY-based approach as we increase network size is saturated due to limited throughput gain [16]. Compared to XY-tree based approach, the proposed CRA+AFD outperforms by 81%, 82% and 87% in runtime under larger network size of 32x32.…”

Section: Analysis Under Realworld Benchmarksmentioning

confidence: 96%

User Cooperation Network Coding Approach for NoC Performance Improvement

Xue

Bogdan

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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The astonishing rate of sensing modalities and data generation poses a tremendous impact on computing platforms for providing real-time mining and prediction capabilities. We are capable of monitoring thousands of genes and their interactions, but we lack efficient computing platforms for large-scale (exa-scale) data processing. Towards this end, we propose a novel hierarchical Network-on-Chip (NoC) architecture that exploits user-cooperated network coding (NC) concepts for improving system throughput. Our proposed architecture relies on a light-weighted subnet of cooperation unit routers (CUR) for multicast traffic. Coding network interface (CNI) performs encoding/decoding of NC symbols and shares the data flows among cooperation units(CUs). We endow our proposed NC-based NoC architecture with: (i) a corridor routing algorithm (CRA) for maximizing network throughput and (ii) an adaptive flit dropping (AFD) scheme to mitigate congestion, branch-blocking and deadlock at run-time. The experimental results demonstrate that our proposed platform offers up to 127X multicast throughput improvement over multiple-unicast and XY tree-based multicast under synthetic collective traffic scenario. We have evaluated the proposed platform with different realworld benchmarks under network sizes of 4x4 to 32x32. Simulation results show 21%−91% latency improvement and up to 25X runtime reduction over conventional mesh NoC performing genetic-algorithm based protein folding analysis. FPGA implementation results show minimal overhead.

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Section: Analysis Under Realworld Benchmarksmentioning

confidence: 96%

User Cooperation Network Coding Approach for NoC Performance Improvement

Xue

Bogdan

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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“…Scheduling algorithms have a profound impact on MPSoC systems performance, energy efficiency and reliability [12,16]. Numerous task mapping/scheduling schemes have been proposed for MPSoC based systems using different optimization techniques, such as integer linear programming [2], genetic algorithm [17], and ant colony optimization [15]. The technique proposed by [2], aims to minimize energy consumption of heterogeneous MPSoCs.…”

Section: Related Workmentioning

confidence: 99%

“…The technique proposed by [2], aims to minimize energy consumption of heterogeneous MPSoCs. Another technique proposed by [17] used genetic algorithm to improve energy efficiency and achieved higher bandwidth for the NoC-based MPSoC systems. The authors in [15] and [18] developed an ant colony optimization (ACO) based scheme with the aim of minimizing computational overhead of MPSoCs.…”

Section: Related Workmentioning

confidence: 99%

“…[24] Focuses on integrating task mapping, task ordering and voltage scaling. To take advantage of the different computational resources available on a given system, researchers in [17,25,26] propose parallel genetic algorithms (PGA). In [17] PGA measures the fitness value of each person in a single population leveraging highly parallel processors, such as the master-slave-based GA platform.…”

Section: Related Workmentioning

confidence: 99%

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Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

et al. 2021

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Minimizing execution time, energy consumption, and network load through scheduling algorithms is challenging for multi-processor-on-chip (MPSoC) based network-on-chip (NoC) systems. MPSoC based systems are prevalent in high performance computing systems. With the increase in computing capabilities of computing hardware, application requirements have increased many folds, particularly for real world scientific applications. Scheduling large scientific workflows consisting hundreds and thousands of tasks consume significant amount of time and resources. In this article, energy aware parallel scheduling techniques are presented primarily aimed at reducing the algorithm execution time while considering network load. Experimental results reveal that the proposed parallel scheduling algorithms achieve significant reduction in execution time.

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“…In the work [83], a multi-objective ACO based approach is applied to discover the optimal solution for mapping that optimized the energy consumption and hotspot temperature. A hierarchical parallel genetic algorithm (HPGA) has been proposed for multi-core System-on-Chip (SoC) in [84], a new architecture consists of two multiplexing schemes specifically dynamic injection bandwidth multiplexing (DIBM) and time-division based island multiplexing (TDIM) with a task-aware adaptive routing algorithm presented to enhance speedup and minimize the hardware overhead. A quick summary of different transformative heuristic techniques is presented in Table 4.…”

Section: I) Transformative Heuristicsmentioning

confidence: 99%

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

et al. 2020

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Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. I. INTRODUCTION System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]-[7] are published in general and textbooks are also available on the topic [8]-[10]. There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut. papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. A. MOTIVATION AND SCOPE Mostly synthetic traffic patterns are used to imitate the functionalities of rea...

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An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms

Cited by 23 publications

References 11 publications

User Cooperation Network Coding Approach for NoC Performance Improvement

User Cooperation Network Coding Approach for NoC Performance Improvement

Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

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