An efficient NoC router by optimal management of buffer read and write mechanism

Fard, Elnaz Shafigh; Jamali, Mohammad Ali Jabraeil; Màsdàrí, Mohàmmàd; Majidzadeh, Kambiz

doi:10.1016/j.micpro.2022.104440

Cited by 7 publications

(6 citation statements)

References 10 publications

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“…Our router utilizes 65.9% fewer register resources and 65.1% fewer LUT resources than the router in [19]. In comparison to routers mentioned in the literature-EDVC F-R/W, ViChaR, and CDVC-our design reduces register resource utilization by 2.3%, 58.5%, and 0.2%, and LUT resource utilization by 0.3%, 26.7%, and 20.8%, respectively [18]. While our router shows an 11.9% increase in register resource consumption compared to the asynchronous router presented by Patil et al, it exhibits a 2.4% reduction in LUT resource usage [17].…”

Section: Electric Router Structurementioning

confidence: 86%

“…Upon the transmission of a routing request signal from the processing meta-cluster, the data packet is placed into the dynamic buffer, awaiting the router's allocation of the routing path. Moving on to the performance analysis of the shunt router, Table 1 presents a comparison of hardware resource utilization between the offload router designed in this study and the on-chip hybrid router proposed in [17][18][19]. Our router utilizes 65.9% fewer register resources and 65.1% fewer LUT resources than the router in [19].…”

Section: Electric Router Structurementioning

confidence: 99%

“…Moving on to the performance analysis of the shunt router, Table 1 presents a comparison of hardware resource utilization between the offload router designed in this study and the on-chip hybrid router proposed in [17][18][19]. Our router utilizes 65.9% fewer register resources and 65.1% fewer LUT resources than the router in [19].…”

Section: Electric Router Structurementioning

confidence: 99%

See 2 more Smart Citations

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Yang,

Li,

et al. 2024

Electronics

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Addressing challenges regarding Hybrid Optoelectronic Network-on-Chip systems, such as congestion control, their limited adaptability, and their inability to facilitate optoelectronic co-simulation, this study introduces an adaptive hybrid optoelectronic interconnection shunt structure tailored for reconfigurable array processors. Within this framework, an adaptive shunt routing algorithm and a low-loss non-blocking five-port optical router are developed. Furthermore, an adaptive hybrid optoelectronic interconnection simulation model and a performance statistical model, established using SystemVerilog and Verilog, complement these designs. The experimental results showcase promising enhancements: the designed routing algorithm demonstrates an average 17.5% improvement in mitigating congestion at network edge nodes; substantial reductions in the required number of cross waveguides and micro-ring resonators for optical routers lead to an average path insertion loss of only 0.522 dB. Moreover, the hybrid optoelectronic interconnection performance statistical model supports the design of routing strategies and topology structures, enabling resource usage, power consumption, insertion loss, and other performance metrics to be accurately assessed.

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Section: Electric Router Structurementioning

confidence: 86%

Section: Electric Router Structurementioning

confidence: 99%

Section: Electric Router Structurementioning

confidence: 99%

See 1 more Smart Citation

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Yang,

Li,

et al. 2024

Electronics

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show abstract

“…In order to evaluate the mentioned arbitration scheme, the input port in the router is needed, which [27] has been used to read and write part of the input port from/to the buffer. One of the advantages of this method is the use of a table and two simple read and write circuits.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…For the input port of this type of arbitration, the input port of the method mentioned in [27] has been used. So that each it is stored in one of the virtual channels when entering after checking the buffer slot table and the emptiness of each section based on the write pointer and header it.…”

Section: Proposed Methodsmentioning

confidence: 99%

RR-SFVP: Design of arbitration unit based on Round Robin method with Strong Fairness and Variable Priority for NoC Router

Fard

Jamali

Màsdàrí

et al. 2022

Preprint

Self Cite

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Network on chip (NoC) is one of the communicative structures for multiple cores that has scalability. In designing the NoC micro-router architecture, the arbitration unit is very important due to its significant impact on performance, chip occupation level and NoC power consumption. In this paper, a router arbitration architecture is proposed with a combination of variable priority arbitration and Round Robin. In this architecture, arbitration examines the requests of other channels based on the Round Robin index after requesting the flit to exit the virtual channel in addition to checking the availability of the relevant virtual channel.The simulation results show that the architecture of the RR-SFVP arbitration unit compared to the standard RR method, is 13.7% smaller in area and has 5.7% less power consumption and 53.7% less critical path delay.

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Mapping of Cores onto Network on Chip Architectures by Hierarchical Genetic Evolution Algorithm

Pan¹

2023

Lecture Notes in Electrical Engineering

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An efficient NoC router by optimal management of buffer read and write mechanism

Cited by 7 publications

References 10 publications

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

RR-SFVP: Design of arbitration unit based on Round Robin method with Strong Fairness and Variable Priority for NoC Router

Mapping of Cores onto Network on Chip Architectures by Hierarchical Genetic Evolution Algorithm

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