An efficient power-area-delay modulo 2&lt;sup&gt;n&lt;/sup&gt;&amp;#x2212;1 multiplier

Timarchi, Somayeh; Fazlali, Mahmood

doi:10.1109/cads.2010.5623593

2010 15th CSI International Symposium on Computer Architecture and Digital Systems 2010

DOI: 10.1109/cads.2010.5623593

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An efficient power-area-delay modulo 2<sup>n</sup>−1 multiplier

Somayeh Timarchi

Mahmood Fazlali

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Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

Dipto

Sorwar

Sojib

et al. 2020

2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT)

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An efficient power-area-delay modulo 2<sup>n</sup>−1 multiplier

Cited by 2 publications

References 10 publications

Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

A unified addition structure for moduli set {2<sup>n</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>+1} based on a novel RNS representation

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An efficient power-area-delay modulo 2<sup>n</sup>&#x2212;1 multiplier

Cited by 2 publications

References 10 publications

Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

A unified addition structure for moduli set &#x007B;2<sup>n</sup>&#x2212;1, 2<sup>n</sup>, 2<sup>n</sup>+1&#x007D; based on a novel RNS representation

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An efficient power-area-delay modulo 2<sup>n</sup>−1 multiplier

A unified addition structure for moduli set {2<sup>n</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>+1} based on a novel RNS representation