An efficient run-time router for connecting modules in FPGAS

Surís, Jorge A.; Patterson, Cameron; Athanas, Peter

doi:10.1109/fpl.2008.4629919

Cited by 21 publications

(7 citation statements)

References 8 publications

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“…[29], [38]), online routing is not sufficiently supported by current design tools. Technically, it is possible to directly use FPGA's routing resources by activating the appropriate Programmable Interconnection Points (PIP) as presented in [23]. In this work, the authors could generate a database with the routing resources information, which is obtained from the netlist file generated by Xilinx XDL tool.…”

Section: Online Routingmentioning

confidence: 99%

“…Second, the fine-grained access to the bitstream is nowadays not possible, except to those bits whose function has been previously identified by reverse-engineering [19,20,22,23] or by using Xilinx provided JBits API [24,25]. While the first two referenced efforts obtain this information by comparing the bitstream changes after specific design modifications, the last three works parse the EDIF-like FPGA fabric netlist file generated by Xilinx Design Language (XDL) tool.…”

Section: The Scenario Defined By Current Fpgasmentioning

confidence: 99%

See 1 more Smart Citation

A Roadmap for Autonomous Fault-Tolerant Systems

Iturbe

Benkrid

Arslan

et al. 2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain its functionality. This work analyzes how AFTS could be built, specifically focusing on hardware platform dependant issues, and gives an overview of the state-of-the-art in this field, which is still in its infancy. Three technological levels are used for classifying the research efforts conducted to date. By describing the current state-of-the-art and the constraints imposed by current technology, this work tries to envision future trends towards the ultimate objective of achieving a fully-adaptive system capable of modifying its architecture on-the-fly as needed. Finally, the general structure and organization of a Reliable Reconfigurable Real-Time Operating System (R3TOS) is presented. This OS aims at making the aforementioned adaptability easily exploitable by future commercial applications.

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Section: Online Routingmentioning

confidence: 99%

Section: The Scenario Defined By Current Fpgasmentioning

confidence: 99%

A Roadmap for Autonomous Fault-Tolerant Systems

Iturbe

Benkrid

Arslan

et al. 2010

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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“…Reference [11] shows work in developing a JIT hardware compiler, aimed at solving simplified place and route problems at run time. Reference [12] is a paper that also falls in this category. They simplify the routing problem by reducing the complexity of the routing architecture.…”

Section: Parameterised Configurations and Tmapmentioning

confidence: 99%

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

Davidson

Abouelella

Bruneel

et al. 2012

International Journal of Reconfigurable Computing

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Parameterised reconfiguration is a method for dynamic circuit specialization on FPGAs. The main advantage of this new concept is the high resource efficiency. Additionally, there is an automated tool flow,TMAP, that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. We will start by explaining the core principles behind the dynamic circuit specialization technique. Next, we show the possible gains in encryption applications using an AES encoder. Our AES design shows a 20.6% area gain compared to an unoptimized hardware implementation and a 5.3% gain compared to a manually optimized third-party hardware implementation. We also usedTMAPon a Triple-DES and an RC6 implementation, where we achieve a 27.8% and a 72.7% LUT-area gain. In addition, we discuss a run-time reconfigurable DNA aligner. We focus on the optimizations to the dynamic specialization overhead. Our final design is up to 2.80-times more efficient on cheaper FPGAs than the original DNA aligner when at least one DNA sequence is longer than 758 characters. Most sequences in DNA alignment are of the order 213.

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“…The Wires-on-Demand RTR framework [17] includes a channel router, which uses a simplified resource database and simple algorithms to find local routes between blocks while requiring relatively few computational resources: memory consumption during execution is three orders of magnitude smaller and execution is four orders of magnitude faster than when using vendor tools (over a set of seven small benchmarks). The reported implementation results were obtained on a Pentium 4 PC (2.8 MHz); the possibility of running in an embedded system is mentioned, but no results are reported.…”

Section: Related Workmentioning

confidence: 99%

Run-time generation of partial FPGA configurations for subword operations

Silva

Ferreira

2012

Microprocessors and Microsystems

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a b s t r a c tInstructions for concurrent processing of smaller data units than whole CPU words are useful in areas like multimedia processing and cryptography. Since the processors used in FPGA-based embedded systems lack support for such applications, this paper proposes mapping sequences of subword operations to a set of hardware components and generating the corresponding FPGA partial configurations at run-time. The technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. New partial configurations for circuits implementing sets of subword operations are created by merging together the relocated partial configurations of the hardware components (from a predefined library), and the configurations of the switch matrices used for the connections between the components. The paper presents and discusses results obtained for a 300 MHz PowerPC CPU in a Virtex-II Pro platform FPGA. For the set of benchmarks analyzed, the complete configuration creation process takes between 1 s and 24 s. The run-time generated hardware versions achieve speed-ups between 11 and 73 over the software versions.

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An efficient run-time router for connecting modules in FPGAS

Cited by 21 publications

References 8 publications

A Roadmap for Autonomous Fault-Tolerant Systems

A Roadmap for Autonomous Fault-Tolerant Systems

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment

Run-time generation of partial FPGA configurations for subword operations

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