An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

Tamimi, Sajjad; Ebrahimi, Zahra; Khaleghi, Behnam; Asadi, Hossein

doi:10.1109/tcad.2018.2812118

Cited by 21 publications

(8 citation statements)

References 41 publications

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“…Furthermore, we plan to design an approximate Arithmetic Logic Unit (ALU) and assess its applicability in the data-path of soft processors such as RISC-V. In fact, RAPID bears a great potential to be deployed in the mantissa multiplier/divider which consume more than 95% of the total area and power in the floating point unit (in which division latency is up to 35× of addition operation) [20,73]. Recently, this track has attracted noticeable attention, especially due to the ever-growing usage of 3D computer graphics [74,75].…”

Section: Discussionmentioning

confidence: 99%

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Ebrahimi

Zaid

Wijtvliet

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The rapid updates in error-resilient applications along with their quest for high throughput has motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies have proposed various imprecise functional techniques, albeit posed with three shortcomings: first, most existing inexact multipliers and dividers are specialized for Application-Specific Integrated Circuit (ASIC) platforms. Therefore, due to the architectural differences of underlying building blocks in FPGA and ASIC, ASIC-customized designs have not yielded comparable improvements when directly synthesized and ported to FPGAs. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multi-kernel application. Moreover, the end-to-end assessment is adopted on the Quality of Results (QoR), but not on the overall gained performance. Finally, existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., divisionincluded applications. In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architectures, customized for FPGAs. The proposed units efficiently utilize 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach, but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division.Experimental results obtained with Xilinx Vivado demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts. In particular, 4-stage pipelined architecture of 32-bit RAPID multiplier (divider) enables 3.3× (5.1×) higher throughput, 2.3× (6.8×) higher throughput/Watt, and 52% (31%) savings of LUTs, over their 4-stage pipelined, accurate IP counterparts. Moreover, the end-to-end evaluations of non-pipelined RAPID, deployed in three multi-kernel applications in the domains of bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) indicate up to 35%, 33%, and 45% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over accurate kernels, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https://cfaed.tu-dresden.de/pd-downloads.

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Section: Discussionmentioning

confidence: 99%

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Ebrahimi

Zaid

Wijtvliet

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In this paper [7], an SRAM based reconfigurable architecture used to minimize the usage of units and low fragmentation. Also integrating low utilized LUTs for reconfigurability.…”

Section: Related Workmentioning

confidence: 99%

“…Conventional reconfigurable architectures have some drawbacks like application domain is not generic, power inefficient [10]- [13]. [7] proposes a reconfigurable architecture focusing on efficient area and power for soft core processors by making use of low utilization and fragmented functional units. To find the low utilization and fragmented functional units, benchmarks are used.…”

Section: Related Workmentioning

confidence: 99%

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

Preethi¹,

G²,

Augustine³

et al. 2022

INDJCSE

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In microprocessor architecture, amid a few blocks outcome of the optimized sorting algorithm has proved its impact on the results. Sorters can be implemented in domains that includes data centers, cloud computing servers for IoT applications. Sorters can be implemented on hardware, by deploying the developed sorter on Field Programmable Gate Array (FPGA). By contrasting factors like power consumption, implementation time, and implementation space with those of the proposed algorithm, it is possible to show the shortcomings of existing sorters like Bubble sort, Bitonic sort, and Odd-Even sort. This approves that the sorter with higher capability will perform better for sorting involving large numbers, this helps in designing of large-scale sorting for aforementioned applications. Few sorters were compared based on the parameters and it was concluded that comparison-free odd-even was having upper hand. Hence, the optimized sorter was implemented on the MicroBlaze, which is based on RISC-V architecture.

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“…Considering the environmental complexity and high cost of space applications, the devices we adopt in the spacecraft should be reconfigurable. FPGA has attracted more and more attention and has been applied to many space programs [1]- [4]. However, there exist many high energy particles in the space environment, and the interaction of high energy particles with electronic components will cause SEEs (Single Event Effects).…”

Section: Introductionmentioning

confidence: 99%

“…The SEE happens when the collected fraction of the charge liberated by the high energy particle might be larger than the electric charge stored on a sensitive node [5]. There are many manifestations of SEEs, such as SEU, MEU, SET, SEFI, etc., which will cause damage to the FPGA circuits to different degrees [4]- [6], [6]- [9].…”

Section: Introductionmentioning

confidence: 99%

SEE Fault Sensitivity Analysis and Security Reinforcement Design for FPGA Circuits Based on Complex Network

et al. 2020

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There may exist many high-energy particles in spacecraft, so the FPGA circuits design needs corresponding sensitivity analysis and security reinforcement of anti-SEE (Single-event effects). However, it may be impractical to perform such measures to all modules of FGPA circuits due to limited resources. To identify the key modules which have a vital impact on the design and operation of FPGA circuits in spacecraft, this paper presents a novel scheme based on complex network for modeling the modules considering both the circuit functional structure and signal interaction relationship between modules. First, complex networks like MSN (Module Structure Network) and SFN (Signal Flow Network) are established to identify modules by treating each module as a node, and indicators including degree centrality (DC), betweenness centrality (BC), clustering coefficient (CC), etc., are calculated. Then, an entropy-weight method (EWM) is utilized to calculate the indicators comprehensively for identifying key modules. Next, network efficiency and sensitivity analysis are performed for failure modes. Finally, a case study is carried out, demonstrating the effectiveness of the proposed scheme for the key module identification. This work provides useful technical support for engineers in spacecraft FPGA circuits design and performance enhancement.INDEX TERMS Complex network, FPGA circuits, SEE sensitivity analysis, entropy-weight method.

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An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

Cited by 21 publications

References 41 publications

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

SEE Fault Sensitivity Analysis and Security Reinforcement Design for FPGA Circuits Based on Complex Network

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