An efficient synchronization technique for multiprocessor systems on-chip

Monchiero, Matteo; Palermo, Gianluca; Silvano, Cristina; Villa, Oreste

doi:10.1145/1147349.1147357

Cited by 14 publications

(4 citation statements)

References 23 publications

(28 reference statements)

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“…Monchiero et al [2] present an augmented global memory controller, the Synchronisation-operation Buffer (SB), to reduce contention for busy-waiting synchronisation primitives in future mobile systems with complex Network-on-Chips (NoCs). Their main focus is on reducing contention, and therefore enabling an efficient use of busy-waiting synchronisations like spin locks.…”

Section: Related Workmentioning

confidence: 99%

Time analysable synchronisation techniques for parallelised hard real-time applications

Gerdes¹,

Ungerer²,

Rochange³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software synchronisation techniques can be implemented in a time analysable way based on the proposed hardware primitives. We choose to implement the hardware synchronisation primitives in the memory controller for two reasons. Firstly, we remove pessimism in the WCET analysis of parallelised HRT applications. Secondly, we enable that the implementation of synchronisation techniques is mostly independent of the chosen instruction set architecture (ISA) which allows to use the existing ISAs without enhancements. We analyse the presented synchronisation techniques with the static worstcase execution time (WCET) analysis tool OTAWA. In summary, our specifically engineered synchronisation techniques yield a tremendous gain on the WCET of parallelised HRT applications. I. INTRODUCTIONFor a long time research in parallel applications and architectures was bound to the domain of high-performance computing. With the upcoming of multi-core processors, parallelisation became also important in other domains, namely desktop end-user systems and embedded systems as well. However, embedded systems have different needs and must fulfil other requirements than high-performance systems. Today's HRT applications in the automotive, avionic or machinery industry are executed on single-core processors. The new trend of using multi-cores in safety-critical domains sparks off research on running HRT tasks in parallel with other tasks to execute mixed-critical application workloads. Our research goes even one step further: we target multi-core execution of parallelised HRT tasks without sacrificing timing guarantees.In this paper, we focus on the timing predictability of synchronisation in parallelised HRT applications using the static WCET analysis tool OTAWA [1]. The contributions of this paper are as follows: we show that specifically engineered software synchronisation techniques, busy-waiting as well as blocking synchronisation methods, are timing analysable. We assess these synchronisation primitives and their hardware respectively software implementation with respect to their impact on the WCET, and the possible gain for the WCET of parallelised HRT applications.The presented synchronisation techniques can be implemented independently of the ISA, as the logic for the hardware synchronisation primitives is nested in the memory controller.

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Section: Related Workmentioning

confidence: 99%

Time analysable synchronisation techniques for parallelised hard real-time applications

Gerdes¹,

Ungerer²,

Rochange³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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show abstract

“…Unlike MCS Locks, in QOLB the queue is implemented entirely in hardware at the cache controller level. The Synchronization-operation Buffer (SB) [16] is a hardware module which augments the memory controller to queue and manage lock operations issued by the threads. QOLB reports non-negligible performance gains when compared to MCS Locks.…”

Section: Related Workmentioning

confidence: 99%

GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs

́n

́ndez

Acacio

2011

2011 IEEE International Parallel &Amp; Distributed Processing Symposium

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Synchronization is of paramount importance to exploit thread-level parallelism on many-core CMPs. In these architectures, synchronization mechanisms usually rely on shared variables to coordinate multithreaded access to shared data structures thus avoiding data dependency conflicts. Lock synchronization is known to be a key limitation to performance and scalability. On the one hand, lock acquisition through busy waiting on shared variables generates additional coherence activity which interferes with applications. On the other hand, lock contention causes serialization which results in performance degradation. This paper proposes and evaluates GLocks, a hardware-supported implementation for highly-contended locks in the context of many-core CMPs. GLocks use a tokenbased message-passing protocol over a dedicated network built on state-of-the-art technology. This approach skips the memory hierarchy to provide a non-intrusive, extremely efficient and fair lock implementation with negligible impact on energy consumption or die area.A comprehensive comparison against the most efficient shared-memory-based lock implementation for a set of microbenchmarks and real applications quantifies the goodness of GLocks. Performance results show an average reduction of 42% and 14% in execution time, an average reduction of 76% and 23% in network traffic, and also an average reduction of 78% and 28% in energy-delay 2 product (ED 2 P) metric for the full CMP for the microbenchmarks and the real applications, respectively. In light of our performance results, we can conclude that GLocks satisfy our initial working hypothesis. GLocks minimize cache-coherence network traffic due to lock synchronization which translates into reduced power consumption and execution time.

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“…Such algorithms rely on cache-coherency protocols like MESI or MOESI [HP03,SS86]. A different approach is described in [MPSV06] in which a MPSoC with private off-chip memory and a small shared on-chip memory is presented. A dedicated hardware block, the synchronization-operation buffer (SB), augments the memory controller and stores requests issued by the processing elements.…”

Section: Background and Related Workmentioning

confidence: 99%

“…In MPSoCs, multiple heterogeneous processing elements like processor cores or application specific accelerators are connected using a network-on-chip (NoC) and combined on a single chip with integrated memory components. An example for such a MPSoC architecture is GRAPES [MPSV06] with 4 to 16 cores. [Dua09] nisms for memory management are de facto standard.…”

Section: Introductionmentioning

confidence: 99%

Efficient Synchronization Techniques in a Decentralized Memory Management System Enabling Shared Memory

Mattes¹,

Schindewolf²,

Sedler³

et al. 2011

PARS-Mitteilungen

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Abstract:The rising integration level enables combining more logic on a single chip. This is exploited in multiprocessor systems-on-chip (MPSoCs) or manycore research prototypes such as the Intel SCC. These platforms offer access to shared memory over a limited number of controllers which may lead to congestion. In order to scale the memory with the core count, the memory management must become more flexible and distributed in nature. In the near future decentralized systems with multiple selfmanaging memory components will arise.The problem tackled in this paper is how to realize synchronization mechanisms for coincident access to shared memory in such a decentralized memory management system. Furthermore, improvements of the distributed synchronization mechanism are integrated and evaluated. To speed up the synchronization, additional logic in the form of a locks queue, is added. In order to reduce the network traffic this is combined by extending the synchronization protocol with exponential backoff. In the evaluation, side effects of combining both techniques are discussed and explained.

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An efficient synchronization technique for multiprocessor systems on-chip

Abstract: Abstract

Cited by 14 publications

References 23 publications

Time analysable synchronisation techniques for parallelised hard real-time applications

Time analysable synchronisation techniques for parallelised hard real-time applications

GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs

Efficient Synchronization Techniques in a Decentralized Memory Management System Enabling Shared Memory

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