An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects

Sanyal, Alodeep; Rastogi, Ashesh; Chen, Wei; Kundu, Sandip

doi:10.1109/tc.2010.75

Cited by 19 publications

(10 citation statements)

References 15 publications

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“…Then the overall gate leakage is the sum of the gate current in each transistor. Thus, I G can be expressed using different current component [28] is given as…”

Section: Leakage Current and Fs-s Operationmentioning

confidence: 99%

State retained dual‐ V _th feedback sleeper‐stack for leakage reduction

Krishnakumar

2018

IET Computers & Digital Techniques

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With the advent of nanoscale devices, due to the problems of leakage power has grown enormously. Reducing leakage power is one of the main challenges in the design of low power circuits. This study presents a delay efficient circuit level leakage reduction technique, which uses dual-V th named 'Feedback Sleeper-Stack (FS-S)' for deep submicron (DSM) technology. FS-S is proposed in order to reduce leakage power dramatically while saving exact logic state. An analytical RC delay model of the FS-S is derived. Comparisons are then carried out in terms of leakage power, total power, delay, area, and power-delay product to the available leakage reduction techniques. 45 nm BSIM4 Predictive Technology Model parameters are used to estimate the changes in power and delay. FS-S is applied to three generic logic circuits to show that the proposed technique is suitable for general logic circuits. Results show that chain of four inverters, NAND3 gate, and C17 circuit with dual-V th FS-S give 15, 62, and 90% performance levels, respectively, over base case circuit under iso-area condition.

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“…Then the overall gate leakage is the sum of the gate current in each transistor. Thus, I G can be expressed using different current component [28] is given as…”

Section: Leakage Current and Fs-s Operationmentioning

confidence: 99%

State retained dual‐ V _th feedback sleeper‐stack for leakage reduction

Krishnakumar

2018

IET Computers & Digital Techniques

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“…They go from enhancing possibilities given by standard models, through implementing entirely new ones to constructing new macro-models formed by standard models. From the recent publications, we can point out the following articles [1][2][3][4][5][6][7][8][9] that are entirely or partly focused on model improvement in the SPICE simulators. The second direction of the development is targeted to algorithms used during simulation.…”

Section: Introductionmentioning

confidence: 99%

Efficient Procedure Improving Precision of High Conditioned Matrices in Electronic Circuits Analysis

Cerny¹,

Dobeš²,

Banas³

2018

RADIOENGINEERING

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In this article, we propose several improvements that could be done to SPICE simulator. The first is based on a functional implementation of device models. The advantages of functional implementation are demonstrated on basic Shichman-Hodges model of MOS transistor. It starts with a description of primary algorithms used in SPICE simulator for the solution of circuits with nonlinear devices and identify the problems that can occur during simulations. Main part of the article is devoted to improved factorization procedure for simulation of the nonlinear electronic circuits. The primary intention of the proposed method is to increase final precision of the result in a case of high condition linear systems. The procedure is based on a use of the iterative methods for solution of nonlinear and linear equations. Utilizing those methods for one iterative process helps to reduce memory consumption during simulation computation, and it can significantly improve simulation precision. The procedure allows to use enumeration with definable precision in a very efficient way.

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“…Leakage current has been growing substantially as circuits are built in advanced process technologies that continually shrink the device geometries. Static power consumption, due to leakage, now accounts for 20 to 25 percent of the total power consumption of designs being fabricated in the most advanced process technologies [6] [21], There are different mechanisms that cause leakage current: gate-substrate tunneling, subthreshold conduction through "off* transistors, reverse biased diodes, etc. The two biggest contributors to leakage power consumptions are gate-to-substrate tunneling and subthreshold leakage [6], Gate to substrate leakage occurs when electrons tunnel through the gate oxide to the substrate.…”

Section: Leakage Powermentioning

confidence: 99%

“…Power dissipation due to gate leakage, gate-substrate tunneling, forms the majority of the static power consumption when gate oxide thickness is less than 20 Angstroms [7], Subthreshold conduction occurs when the transistor is "off', when VGS < Vthreshoid, but small amounts of current flow through the transistor due to the weak inversion layer. Subthreshold current rises exponentially with temperature and gate-tosource voltage [6], High threshold voltage transistors will be exclusively used when implementing the flip-flops to minimize leakage power.…”

Section: Leakage Powermentioning

confidence: 99%

“…// VerilogA for flops, data, veriloga "include "constants.vams" "include "disciplines.vams" module data(dataout); output [7:0] analog begin @(initial_step) begin randdata = 0; seed=0; end @(timer(start, period)) begin x = abs($random(seed) % 100); if (x<enable_asserted) begin rand_data=l; end else begin randdata = 0; end $strobe ("Generated Enable Value is %b , %g\t", rand data, Sabstime); end //V(data out) <+ transition(rand_data,0.2n,0.2n); V(dataout) <+ rand data; end endmodule Appendix B Enable Generator Verilog-A Code // VerilogA for flops, prbs, veriloga "include "constants.vams" "include "disciplines.vams" module prbs(dataout); output [7:0] [3]) <+ rand_data [3]; V(data out [4]) <+ rand_data [4]; V(data_out [5]) <+ rand_data [5]; V(data_out [6]) <+ rand_data [6]; V(data_out [7]) <+ rand_data [7]; end endmodule // VerilogA for flops, prbs with enable, veriloga 'include "constants.vams" 'include "disciplines.vams" module prbs_with_enable(data_out,enable); output [7:0]…”

Section: Appendix B Enable Generator Verilog-a Codementioning

confidence: 99%

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Low power flip-flop analysis and design for use in network processors

Arunachalam¹

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The author has granted a nonexclusive license allowing Library and Archives Canada to reproduce, publish, archive, preserve, conserve, communicate to the public by telecommunication or on the Internet, loan, distribute and sell theses worldwide, for commercial or noncommercial purposes, in microform, paper, electronic and/or any other formats. L'auteur a accorde une licence non exclusive permettant a la Bibliotheque et Archives Canada de reproduire, publier, archiver, sauvegarder, conserver, transmettre au public par telecommunication ou par Nntemet, preter, distribuer et vendre des theses partout dans le monde, a des fins commerciales ou autres, sur support microforme, papier, electronique et/ou autres formats. The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. L'auteur conserve la propriete du droit d'auteur et des droits moraux qui protege cette these. Ni la these ni des extraits substantiels de celle-ci ne doivent etre imprimis ou autrement reproduits sans son autorisation. In compliance with the Canadian Privacy Act some supporting forms may have been removed from this thesis. While these forms may be included in the document page count, their removal does not represent any loss of content from the thesis. Conformement a la loi canadienne sur la protection de la vie privee, quelques formulaires secondaires ont ete enlev §s de cette these. Bien que ces formulaires aient inclus dans la pagination, il n'y aura aucun contenu manquant.

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An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects

Cited by 19 publications

References 15 publications

State retained dual‐ V _th feedback sleeper‐stack for leakage reduction

State retained dual‐ V _th feedback sleeper‐stack for leakage reduction

Efficient Procedure Improving Precision of High Conditioned Matrices in Electronic Circuits Analysis

Low power flip-flop analysis and design for use in network processors

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An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects

Cited by 19 publications

References 15 publications

State retained dual‐ V th feedback sleeper‐stack for leakage reduction

State retained dual‐ V th feedback sleeper‐stack for leakage reduction

Efficient Procedure Improving Precision of High Conditioned Matrices in Electronic Circuits Analysis

Low power flip-flop analysis and design for use in network processors

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State retained dual‐ V _th feedback sleeper‐stack for leakage reduction

State retained dual‐ V _th feedback sleeper‐stack for leakage reduction