An Efficient Time Annotation Technique in Abstract RTOS Simulations for Multiprocessor Task Migration

Zabel, Henning; Müller, Wolfgang

doi:10.1007/978-0-387-09661-2_18

Cited by 8 publications

(9 citation statements)

References 4 publications

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“…Since the actual iteration count of loops is captured during SystemC simulation, we estimate the time of one iteration per loop at this stage. This is later time accumulated with SystemC simulations with timed back annotation [13].…”

Section: B Graphical Representation and Compaction For Time Estimatimentioning

confidence: 99%

“…In [13], authors divide the basic block for control flow generation. However, the labeling of basic blocks in the source code is done manually which is time consuming and severely limits the approach.…”

Section: Related Workmentioning

confidence: 99%

“…The process of inserting the consumed CPU time of a particular software block into the source code is referred to as back annotation [13]. The cost estimates and the identifiers written into the XML files are utilized for back annotation.…”

Section: B Graphical Representation and Compaction For Time Estimatimentioning

confidence: 99%

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Automated source code annotation for timing analysis of embedded software

Joy

Becker

Mueller

et al. 2012

2012 18th International Conference on Advanced Computing and Communications (ADCOM)

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Virtual platforms are widely applied for embedded software protoyping and analysis. We introduce here an automatic annotation and estimation technique for the dynamic time analysis of embedded software. The annotation technique automatically inserts marks into the software, which can later be identified at assembler code level in order to back-annotate them with timing or power information. Our graph based technique applies automated labeling of basic blocks to aid in efficient construction of basic blocks for the disassembler. The graph is compacted for efficiency and a novel graph traversal technique is applied to estimate the flow cost. The timing estimates are later back annotated to the source code with the help of identifiers which are then used in SystemC simulations. Our technique can be easily deployed across variety of architectures as it is compiler-independent and does not implement any architecture specific features to estimate the time. The option to back-annotate the timing estimates avoids the requirement to recompile the entire model to get the same information before simulation.

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Section: B Graphical Representation and Compaction For Time Estimatimentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Automated source code annotation for timing analysis of embedded software

Joy

Becker

Mueller

et al. 2012

2012 18th International Conference on Advanced Computing and Communications (ADCOM)

View full text Add to dashboard Cite

show abstract

“…Timing annotations and synchronization within user tasks are handled by a replacement of the SystemC wait(). In [16] an annotation method for time estimation has been presented that supports flexible simulation and validation of real-time constraints for task migration between different target processors. The concept allows preemptive scheduling in the context of priority-based scheduling, supporting nested interrupts.…”

Section: Related Workmentioning

confidence: 99%

A program state machine based virtual processing model in SystemC

et al. 2015

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The Program State Machine (PSM) Model of Computation offers a rich set of modeling elements to describe behavioral and structural hierarchy, concurrency, synchronization, state transitions and timing. With the rising software complexity of today's embedded systems, the use of Real-Time Operating Systems (RTOS) has become state-of-the-art for nearly all System-on-Chip designs. Regrettably, the PSM model itself has insufficient support for the specification of the preemptive dynamic scheduling behavior of an RTOS. In this paper, we propose a model for dynamically dispatching PSM models on a virtual processing element. Our model aims to abstract from the targeted RTOS and the processor core through execution time annotations and a flexible preemptive scheduler model. Mapping a PSM model to a set of scheduled virtual processing elements only requires minor model transformation and enables early exploration of different processing element mappings and scheduling policies. Our virtual processing model for PSMs is realized on top of the SystemC library. We evaluate the proposed virtual processing model using a Canny edge detection filter.

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“…Timing annotations and synchronisation within user tasks is handled by a replacement of the SystemC wait(). In [22] an annotation method for time estimation that supports flexible simulation and validation of real-time-constraints for task migration between different target processors has been presented.…”

Section: Related Workmentioning

confidence: 99%

Distributed Resource-Aware Scheduling for Multi-core Architectures with SystemC

Hartmann

Grüttner

Rettberg

et al. 2010

Distributed, Parallel and Biologically Inspired Systems

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Abstract. With the rise of multi-core platforms even more complex software systems can be implemented. Designers are facing various new challenges during the development of efficient, predictable, and correct applications for such platforms. To efficiently map software applications to these architectures, the impact of platform decisions with respect to the hardware and the software infrastructure (OS, scheduling policies, priorities, mapping) has to be explored in early design phases.Especially shared resource accesses are critical in that regard. The efficient mapping of tasks to processor cores and their local scheduling are increasingly difficult on multi-core architectures. In this work we present an integration of shared resources into a SystemC-based simulation framework, which enables early functional simulation and provides a refinement flow towards an implementation, covering an increasing level of platform details. We propose shared resource extensions towards multicore platform models and discuss which aspects of the system behaviour can be captured.

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An Efficient Time Annotation Technique in Abstract RTOS Simulations for Multiprocessor Task Migration

Cited by 8 publications

References 4 publications

Automated source code annotation for timing analysis of embedded software

Automated source code annotation for timing analysis of embedded software

A program state machine based virtual processing model in SystemC

Distributed Resource-Aware Scheduling for Multi-core Architectures with SystemC

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