An elastic pipeline mechanism by self-timed circuits

Komori, S.; Takata, Hiroshi; Tamura, T.; Asai, F.; Ohno, T.; Tomisawa, O.; Yamasaki, T.; Shima, K.; Asada, Katsuhiko; Terada, Hiroaki

doi:10.1109/4.266

Cited by 21 publications

(4 citation statements)

References 2 publications

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“…Table 1 gives final module resource utilization information on target FPGA proved by Kamran 2006. It is already proved by Shinji Komori, in 1988 that for data driven processors, elastic pipelined causes high processing rate and smooth data stream concurrently. Our design is also meant to get concurrent data for processing for fast and efficient operation.…”

Section: Resource Allocation Resultsmentioning

confidence: 99%

“…In hardware approaches special parallel architectures can be design to accelerate computation suggested by R. J. Gove(1994) and Shinji Komori (1988) et al Parallel video compression algorithms can be implemented using either hardware or software approaches as proved by V. Bhaskaran (1995). These techniques provided the guidelines to deal with digital image compression schemes fro speed and complexity point of view.…”

Section: Introductionmentioning

confidence: 99%

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LSCIC Pre Coder for Image and Video Compression

Kamran¹,

Shi²,

Wang³

2010

Robot Vision

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Section: Resource Allocation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

LSCIC Pre Coder for Image and Video Compression

Kamran¹,

Shi²,

Wang³

2010

Robot Vision

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“…In this paper, the state in which T i,j cannot be maintained at a particular level due to an increase in the pipeline dominance is called an overload. In the elastic pipeline [11] used in the CUE processor, a pipeline overload occurs when the pipeline dominance is above roughly 0.7. Given the above, a real-time processor without software control overhead involving priority scheduling during execution can be created by allocating each program to a PE such that e i,j < D i,j is met and overloads do not occur.…”

Section: Operating Characteristics Of the Cue Processormentioning

confidence: 99%

A program allocation method for real‐time processing based on data‐driven processors

Kurebayashi

Nishikawa

2007

Electron Comm Jpn Pt III

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SUMMARYIn this paper the authors propose a program allocation method for the purpose of achieving real-time processing using a chip multiprocessor-type data-driven processor. The data-driven processor can perform parallel processing of executable processes without interference as long as the pipeline is not overloaded. The turnaround time for the individual processes being subjected to multiprocessing is independent of other processes being executed at the same time, and is maintained as is for the execution time when a single process is executed. Therefore, real time for a program can be estimated, and if the program can be allocated to a process such that overload does not occur, then realtime processing can be achieved without scheduling during execution. In this paper the authors first formalize a program allocation method in a data-driven processor. They then propose a combined method using genetic algorithms and a heuristic algorithm that uses lists as a program allocation method that is better at satisfying the time constraints and offers greater scalability for large-scale program and multiprocessor systems to be subjected to allocation. Finally, the authors use experiments in which a communications protocol process is allocated to verify the effectiveness of their program allocation method. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(6): 48-60, 2007; Published online in Wiley InterScience (www.interscience. wiley.com).

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“…4. This C element generates one-shot ACK signal and performs pseudo4cycle signaling to enhance the transfer speed (6). …”

Section: A Self-timed Fifo Elementmentioning

confidence: 99%

An efficient self-timed queue architecture for ATM switch LSI's

Kondoh

Yamanaka²,

Ishiwaki³

et al.

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94

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A new approach to implement queues for controlling ATM switch LSI is presented. We combined a self-timed FIFO with a search circuit that finds the earliest entry for each output port. Using this architecture, queues provided for each output port can be effectively realized by a single FIFO. The delay priority and multicasting are supported without doubling the number of the queues. This new FIFO can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-pm CMOS process technology. Interstage transfer speed over 500 MHz and cycle time over 125 MHz were obtained.

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An elastic pipeline mechanism by self-timed circuits

Cited by 21 publications

References 2 publications

LSCIC Pre Coder for Image and Video Compression

LSCIC Pre Coder for Image and Video Compression

A program allocation method for real‐time processing based on data‐driven processors

An efficient self-timed queue architecture for ATM switch LSI's

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