An embeddable virtual machine for state space generation

Weber, M.

doi:10.1007/s10009-010-0141-2

Cited by 4 publications

(1 citation statement)

References 17 publications

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“…or design a new one and re-target an existing compiler, or even create a new one. Of the newly-designed virtual machines (and their corresponding instruction sets), the most notable is NIPS VM [11]. Along with other similar designs that emerged from the model checking community, its focus is on fixed-layout, explicitly finite-state processes enriched with non-determinism and synchronisation/communication.…”

Section: Related Workmentioning

confidence: 99%

DiVM: Model checking with LLVM and graph memory

Ročkai

Štill

Černá

et al. 2018

Journal of Systems and Software

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In this paper, we introduce the concept of a virtual machine with graphorganised memory as a versatile backend for both explicit-state and abstractiondriven verification of software. Our virtual machine uses the LLVM IR as its instruction set, enriched with a small set of hypercalls. We show that the provided hypercalls are sufficient to implement a small operating system, which can then be linked with applications to provide a POSIX-compatible verification environment. Finally, we demonstrate the viability of the approach through a comparison with a more traditionally-designed LLVM model checker.

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Section: Related Workmentioning

confidence: 99%

DiVM: Model checking with LLVM and graph memory

Ročkai

Štill

Černá

et al. 2018

Journal of Systems and Software

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Integrating pattern matching and abstract interpretation for verifying cautions of microcontrollers

Nguyễn

Tomita

Endo

et al. 2021

Software Testing Verif & Rel

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Summary Handling hardware‐dependent properties at a low level is usually required in developing microcontroller‐based applications. One of these hardware‐dependent properties is cautions, which are described in microcontrollers hardware manuals. The process of verifying these cautions is performed manually, as there is currently no single tool that can directly handle this task. This research aims at automating the verification of these cautions. To obtain the typical cautions of microcontrollers, we investigate two sections which have a considerable number of required cautions in the hardware manual of a popular microcontroller. Subsequently, we analyse these cautions and categorize them into several groups. Based on this analysis, we propose a semi‐automatic approach for verifying the cautions which integrates two static programme analysis techniques (i.e., pattern matching and abstract interpretation). To evaluate our approach, we conducted experiments with generated source code, benchmark source code, and industrial source code. The generated source code, which was created automatically based on several aspects of the C programme, was used to evaluate the performance of the approach based on these aspects. The benchmark and the industrial source code, which were provided by Aisin Software Co., Ltd., were used to assess the feasibility and applicability of the approach. The results show that all expected violations in the benchmark source code were detected. Unexpected but real violations in the benchmark programme were also detected. For the industrial source code, the approach successfully handled and detected most of the expected violations. These results show that the approach is promising in verifying the cautions.

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Model checking software: on some new waves and some evergreens

Bošnački

Edelkamp

2010

Int J Softw Tools Technol Transfer

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An embeddable virtual machine for state space generation

Cited by 4 publications

References 17 publications

DiVM: Model checking with LLVM and graph memory

DiVM: Model checking with LLVM and graph memory

Integrating pattern matching and abstract interpretation for verifying cautions of microcontrollers

Model checking software: on some new waves and some evergreens

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