An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

Grudowski, P. A.; Dhandapani, V.; Zollner, Stefan; Goedeke, D.; Loiko, K.; Tekleab, D.; Adams, V.; Spencer, G.; Desjardins, H.; Prabhu, L.; Garcia, R.; Foisy, M.; Theodore, D.; Weeks, D.; Thomas, S.G.; Thean, Aaron; White, Bruce

doi:10.1109/soi.2007.4357831

Cited by 13 publications

(16 citation statements)

References 3 publications

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“…Those SiC:P layers were used as embedded sources and drains stressors in high performance n-type MOSFETs. 24 In other studies, substitutional C contents of up to 0.25% were obtained in SiC:As layers grown at 750 • C, ATM with a SiH 2 Cl 2 + SiCH 6 + AsH 3 + HCl chemistry. 25 Figure 7 shows the Si 1-y C y :P growth rate and the layer resistivity associated with these layers, as a function of the F(SiCH 6 )/F(PH 3 ) Mass-Flow Ratio.…”

Section: Sic:p Growth Kinetics and Doping At 700mentioning

confidence: 87%

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Hartmann

Aubin

Barraud

et al. 2016

ECS J. Solid State Sci. Technol.

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We have developed an innovative atmospheric pressure process for the selective co-flow deposition of Si(C):P Raised Sources and Drains (RSDs) at 700°C–800°C. Layers of Si:P were grown with SiH2Cl2, HCl and a PH3 1% in H2 bottle (with no dependence on growth temperature) resulting in a Si:P growth rate that increased as the PH3 mass-flow increased, together with a P+ ion concentration that reached 7 × 1019 cm−3. For even higher phosphine flows, we have switched to PH3 5% in H2 bottles and studied the growth kinetics and n-type doping of Si at 700°C. The Si:P growth rate increased, stabilized then decreased (which is most likely due to surface poisoning) as the PH3 mass-flow increased. This was associated with a sharp increase then a stabilization at nearly 1020 cm−3 of the P+ ion concentration. The resulting Si:P layers were single crystalline and slightly rough. Full selectivity versus SiO2 (isolation) and SiN sidewall spacers was achieved on patterned wafers with this heavily chlorinated chemistry. Finally, we have evaluated the feasibility of adding SiCH6 to the gaseous mixture to obtain SiC:P layers. The substitutional C concentration was rather small (at most 0.55%). Meanwhile, the resistivity was at first stable then increased, while the SiC:P growth rate monotonously decreased as the SiCH6 mass-flow went up.

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Section: Sic:p Growth Kinetics and Doping At 700mentioning

confidence: 87%

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Hartmann

Aubin

Barraud

et al. 2016

ECS J. Solid State Sci. Technol.

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“…24,25 It should be noted that enhanced dopant activation and carbon incorporation can be achieved with advanced annealing techniques such as laser anneal. 26,27 Highresolution X-ray diffraction ͑HRXRD͒ was used to quantify C sub for samples with different C and P concentrations, as shown in Fig. 3.…”

Section: Materials Characterization and Process Optimization Of Silic...mentioning

confidence: 99%

“…Through advanced annealing techniques, the issue of S/D resistance for Si:C S/D can potentially be minimized for further I on enhancement. 12,26,27 Impact of channel orientation design.-To improve I on in nFETs, integration schemes involving different substrate and channel orientations have been proposed. 34 Hybrid Si substrates with different crystal orientations through wafer bonding and selective epitaxy can be used to improve complementary metal-oxide semiconductor performance at the cost of increased process complexity.…”

Section: Strained N-channel Fets With Channel-proximate Silicon-carbo...mentioning

confidence: 99%

Strained n-Channel Field-Effect Transistors with Channel Proximate Silicon–Carbon Source/Drain Stressors for Performance Enhancement

Koh

Wong

Gong

et al. 2010

J. Electrochem. Soc.

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An integration scheme for realizing strained n-channel metal-oxide-semiconductor field-effect transistors ͑nFETS͒ with embedded silicon-carbon ͑e-Si:C͒ source/drain ͑S/D͒ stressors formed in close proximity to the channel was demonstrated. The stressors are termed channel-proximate ͑CP͒ Si:C S/D stressors, whose proximity to the channel improves their effectiveness in contributing to tensile strain in the channel region. Numerical simulation was performed using the finite-element method to assess the strain enhancement due to CP Si:C S/D. Key process development and material characterization were performed to understand the interaction between dopants and substitutional carbon concentration C sub . Unstrained control nFETs, nFETs with conventional Si:C S/D formed after spacers, and nFETs with CP Si:C S/D were fabricated. The nFET with CP Si:C S/D stressors achieved a drive current I on enhancement of ϳ19 and ϳ8% over unstrained nFET and nFET with conventional Si:C S/D, respectively. The impact of channel orientation on I on enhancement was also investigated.Strained silicon metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ have been widely adopted in integrated circuit manufacturing. For n-channel metal-oxide-semiconductor fieldeffect transistors, or nFETs, stress memorization technique ͑SMT͒ 1,2 and silicon nitride etch-stop layer with high tensile stress 3,4 have been employed to induce lateral tensile strain in the silicon channel for enhancement of carrier mobility and drive current I on . Recently, the embedded silicon-carbon ͑e-Si:C͒ source/drain ͑S/D͒ stressor has gained attention as another viable option for strain engineering of silicon nFETs. 5-16 The e-Si:C S/D stressor can be formed using selective epitaxial growth, 5-10,13-15 or by ion implantation of carbon followed by solid-phase epitaxy ͑SPE͒. 11,12 With the scaling down of the gate pitch for higher circuit density, the effective stress in the channel due to various strain engineering schemes generally decreases. As a result, performance degradation associated with stress loss due to pitch scaling can be substantial. 17,18 To maintain or increase the strain effects due to the S/D stressor, solutions such as increasing the substitutional carbon concentration in Si:C S/D, increasing the thickness of the S/D stressor, 19,20 or alteration of the mechanical boundary conditions, e.g., removal of spacers, 21 to increase the channel stress have been demonstrated. To enable further pitch reduction with minimal performance compromise, new techniques to maintain or further enhance the strain in the transistor channel region will be highly desirable.In this paper, we demonstrate an integration scheme for realizing strained nFETs with enhanced strain effects by deploying Si:C S/D stressors in close proximity to the channel, hereafter referred to as channel-proximate ͑CP͒ Si:C S/D stressors. This paper focuses on Si:C S/D formed using carbon implant and SPE and its integration adjacent to the channel. Numerical simulation using the finiteelement meth...

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“…5,11 Si:C S/D stressors have been extensively investigated for application in n-MOSFETs since year 2004. [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] Si:C with high substitutional carbon concentration C sub and high crystalline quality can be selectively grown in S/D regions by ultra high vacuum chemical vapor deposition (UHVCVD) or Reduced Pressure Chemical Vapor Deposition (RPCVD). 11,13,14,[16][17][18][19][20][21] To form embedded Si:C S/D stressors, a S/D recess etch step is usually performed prior to the selective growth process.…”

mentioning

confidence: 99%

“…[11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] Si:C with high substitutional carbon concentration C sub and high crystalline quality can be selectively grown in S/D regions by ultra high vacuum chemical vapor deposition (UHVCVD) or Reduced Pressure Chemical Vapor Deposition (RPCVD). 11,13,14,[16][17][18][19][20][21] To form embedded Si:C S/D stressors, a S/D recess etch step is usually performed prior to the selective growth process. Alternatively, embedded Si:C S/D stressors can also be formed by implantation of carboncontaining ions (Carbon ion C + or molecular ions such as C 7 H 7 + ) followed by solid phase epitaxy (SPE).…”

mentioning

confidence: 99%

Silicon-Carbon Source and Drain Stressors: Carbon Profile Design by Ion Implantation

Zhou

Koh

Tong

et al. 2012

J. Electrochem. Soc.

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We investigated Si:C S/D stressors having a retrograde carbon profile formed by carbon ion implantation and solid phase epitaxy (SPE). The retrograde carbon profile features a 30-nm-thick buried silicon carbon (Si:C) layer that is spatially decoupled from a 10-nm-thick surface layer with high phosphorus concentration. Retrograde carbon profile can increase the dopant activation rate in the Si:C S/D stressors and achieves more than 30% reduction of sheet resistance (R s ) when SPE temperature is lower than 800 • C. Samples with retrograde carbon profile have a lower R s for a given substitutional carbon concentration compared to the uniform carbon profile samples. Nickel monosilicide (NiSi) formed on Si:C S/D with a retrograde carbon profile has a R s which ∼10% lower than that formed on Si:C with uniform C profile.

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An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

Cited by 13 publications

References 3 publications

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Strained n-Channel Field-Effect Transistors with Channel Proximate Silicon–Carbon Source/Drain Stressors for Performance Enhancement

Silicon-Carbon Source and Drain Stressors: Carbon Profile Design by Ion Implantation

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