An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS

Li, Meng; Weijers, Jan-Willem; Derudder, Veerle; Vos, Ilse; Rykunov, Maxim; Dupont, Steven; Debacker, Peter; Dewilde, Andy; Huang, Yuanding; Perre, Liesbet Van der; Thillo, Wim Van

doi:10.1109/asscc.2015.7387473

Cited by 11 publications

(10 citation statements)

References 6 publications

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“…Table II presents a summary of key data and comparisons with a selection of previously published LDPC decoders. A state-of-the-art MSA-based LDPC decoder ASIC implemented in 28 nm technology is presented in [3]. Our implementation achieves 4 times higher area efficiency and over 30 times lower energy per bit.…”

Section: Chip Implementation and Measurement Resultsmentioning

confidence: 99%

“…However, decoders using iterative message-passing algorithms such as the min-sum algorithm (MSA) are very costly in terms of silicon area and power, making performance-cost tradeoffs necessary. Prior decoder implementations have addressed these problems with voltage-frequency scaling (VFS) in conjunction with partially parallel or layered architectures [1] [2] [3], serialized message passing [4], bi-directional message passing circuitry [5], or using refresh-free embedded dynamic random access memory (eDRAM) in lieu of registers [6].…”

Section: Introductionmentioning

confidence: 99%

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A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI

Cushon

Larsson-Edefors

Andrekson

2018

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

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We present a low-density parity check (LDPC) decoder using the adaptive degeneration (AD) algorithm with a (3600, 3000) LDPC code, integrated in 1.85 mm 2 in 28 nm FD-SOI. With early termination and variable latency decoding, this decoder achieves an optimal energy efficiency of 0.16 pJ/bit and information throughput of 13.6 Gbps with a core supply voltage of 0.4 V. At a core supply voltage of 1.0 V, it achieves 0.58 pJ/bit energy efficiency and 181 Gbps throughput. With constant latency equal to the maximum number of iterations, it achieves optimal energy efficiency of 0.52 pJ/bit and information throughput of 7.2 Gbps at a supply voltage of 0.55 V, and 1.9 pJ/bit energy and 24 Gbps throughput at 1.0 V. The net coding gain at a bit error rate of 10 −12 is 8.7 dB.

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Section: Chip Implementation and Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI

Cushon

Larsson-Edefors

Andrekson

2018

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

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“…Based on the channel observation, it is clear that the wireless VR system over 60 GHz RFIC should recover a number of burst errors. For some specifications targeting the high-speed near-field wireless communications, several candidates can support such a channel condition with different types of codes including low-density parity-check (LDPC) codes targeting the data rate of more than 6 Gbps [9][10][11][12]17]. However, the previous standards are normally defined to support various applications and thus they include several complicated processing steps to ensure the data integrity for different transmitting scenarios.…”

Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%

“…FB1 FB2 FB3 High-speed serializer High-speed de-serializer To provide the quantitative comparisons, we summarize the error-correcting performances and the implementation results for different ECC decoding architectures, as depicted in Figure 10 and Table 2, respectively. Compared to the proposed interleaved-BCH code, it is noticeable that the low-rate ECCs for the existing wireless communications, i.e., the 0.5-rate polar code for 5G systems [23] and the 0.5-rate LDPC code for WiGig standards [11,12], provide superior correcting powers, as depicted in Figure 10. However, the baseband systems based on these soft-decision ECCs normally include complicated processing steps associated with high-resolution ADCs, drastically increasing the transmission latency and the energy consumption, as shown in Table 2.…”

Section: Fb0mentioning

confidence: 99%

“…If we directly adopt the high-speed near-field communication standards [6][7][8], however, it is inefficient to give the immersive user-level experience due to the long transmission latency caused by the iterative error recovery algorithms associated with complex interleaving schemes [9][10][11][12]. Supporting the transmission rate of over 6 Gbps, for example, the recent WiGig standard uses a number of baseband operations including the scrambler, the FFT-based processing, the high-speed analog-to-digital conversion, and the iterative low-density parity-check (LDPC) error-correction code (ECC), requiring the transmission delay of more than 5 ms [13].…”

Section: Introductionmentioning

confidence: 99%

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High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

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Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

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Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

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An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS

Cited by 11 publications

References 6 publications

A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI

A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

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