An Energy Efficient AES Encryption Core for Hardware Security Implementation in IoT Systems

Dao, Manh-Hiep; Hoang, Van‐Phuc; Dao, Van-Lan; Tran, Xuan‐Tu

doi:10.1109/atc.2018.8587500

Cited by 16 publications

(12 citation statements)

References 3 publications

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“…The first four bits of the element represent the number of the row of the S-Box while the second four bits represent the number of the column of the S-Box. The value obtained from the S-Box due to the number of the row and the number of the column will replace the previous value of the element [22]. The SubBytes step is shown in Figure 2.…”

Section: The Subbytes Stepmentioning

confidence: 99%

Design and implementation of pipelined and parallel AES encryption systems using FPGA

Nabil

Khalaf

Hassan

2020

IJEECS

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The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the Advanced Encryption Standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.

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Section: The Subbytes Stepmentioning

confidence: 99%

Design and implementation of pipelined and parallel AES encryption systems using FPGA

Nabil

Khalaf

Hassan

2020

IJEECS

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“…In the initial round, the text is Xored with the input key to produce the input of the next round while the second round starts with the subbytes steps [5,23,24].…”

Section: Fig 1 the Aes Encryption Systems Steps Of Each Roundmentioning

confidence: 99%

“…The element of every row is shifted due to the number of the rows, the first row is not shifted, the second row is where one element is shifted to the left, the third row is where the two elements are shifted to the left and the final row is where the three elements are shifted to the left as shown in Fig. 4 [4,5,16,23].…”

Section: B the Shiftraws Stepmentioning

confidence: 99%

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Design and Implementation of Pipelined AES Encryption System using FPGA

Nabil¹,

Khalaf²,

Hassan³

2020

IJRTE

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Nowadays, the data encryption became very important because of the usage of the data transmission in all the filed. The Advanced Encryption Standard (AES) that known as Rijndael algorithm is one of the most common encryption algorithms. The AES consists of 9 rounds in addition to the initial and final rounds that makes the AES consumes much time for encrypting the data. Of course the time consumption is considered one of the problems that face the information security. The more time the encryption system consumes to encrypt the data, the more chances increase for the hackers to break into the system. In this work, we find a new technique that can be used to increase the performance speed of the advanced encryption standard. The proposed algorithm methodology depends on the pipelined processing method for the processing time reduction. The paper includes a discussion of the design, the analysis and the implementation using Field Programmable Gate Array (FPGA) of the pipelined method to reduce the consumed numbers of clocks and speed up the processes. The AES is used to protect information and encrypt sensitive data and used in satellites, missiles, military application and other critical application. The paper describes the AES encryption system algorithm and the implementation of both the normal processing and the pipelined processing, and finally a comparison between the two algorithms.

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“…The block size of each algorithm is 128 bits, and the key length is one of these sizes: 128, 192 or 256 bits. The key length is a symmetric-key technique which utilizes the same key for encrypting and decrypting [6][7][8]. One of the main problems that faces the AES encryption system is the long time consumed to perform the encryption and the decryption processes.…”

Section: Introductionmentioning

confidence: 99%

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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The data encryption is one of the most critical issues in the communication system design. Nowadays, many encryption algorithms are being updated to keep pace with the remarkable progress in the communication field. The advanced encryption standard (AES) is a common algorithm that has proved its efficacy. The main drawback of AES is that it uses too simple algebraic structures, since every block is always encrypted in the same way that makes the hacking process possible if the hacker captures the key and the uses S-Box in the input stage. This especially applies to the unwired communication systems where chances of hacking exceed those found in the wired systems. The paper proposes a security enhancement method that is based on utilizing concatenated AES and international data encryption algorithm (IDEA) algorithms. Upon applying the proposed algorithm, the hacking process becomes a great challenge. The paper incorporates the real-time FPGA implementation of the proposed algorithm in the encryption and the decryption stages. Besides, the paper presents a clear analysis of the system’s performance.

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An Energy Efficient AES Encryption Core for Hardware Security Implementation in IoT Systems

Cited by 16 publications

References 3 publications

Design and implementation of pipelined and parallel AES encryption systems using FPGA

Design and implementation of pipelined and parallel AES encryption systems using FPGA

Design and Implementation of Pipelined AES Encryption System using FPGA

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

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