Design and implementation of pipelined and parallel AES encryption systems using FPGA

Nabil, Mohamed; Khalaf, Ashraf A. M.; Hassan, Sara

doi:10.11591/ijeecs.v20.i1.pp287-299

Cited by 12 publications

(8 citation statements)

References 27 publications

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“…Table 1 illustrates the proposed system's device utilization summary. By comparing the hardware resources of this paper shown in Table 1 with the utilized hardware table in [14], it is evident that the proposed concatenated algorithm consumes more hardware resources than the normal processing. This result is predicated because the paper uses two different concatenated algorithms.…”

Section: Simulation and Resultsmentioning

confidence: 99%

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Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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<span>The data encryption is one of the most critical issues in the communication system design. Nowadays, many encryption algorithms are being updated to keep pace with the remarkable progress in the communication field. The advanced encryption standard (AES) is a common algorithm that has proved its efficacy. The main drawback of AES is that it uses too simple algebraic structures, since every block is always encrypted in the same way that makes the hacking process possible if the hacker captures the key and the uses S-Box in the input stage. This especially applies to the unwired communication systems where chances of hacking exceed those found in the wired systems. The paper proposes a security enhancement method that is based on utilizing concatenated AES and international data encryption algorithm (IDEA) algorithms. Upon applying the proposed algorithm, the hacking process becomes a great challenge. The paper incorporates the real-time FPGA implementation of the proposed algorithm in the encryption and the decryption stages. Besides, the paper presents a clear analysis of the system’s performance.</span>

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Section: Simulation and Resultsmentioning

confidence: 99%

“…Pipelined processing decreased the consumed time, making it less than the time consumed during conducting the normal processing. Mohamed Nabil et al [14], an enhanced processing algorithm based on the parallel processing is presented. The article offers a detailed description of the proposed algorithm methodology.…”

Section: Introductionmentioning

confidence: 99%

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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“…In [23]. In [24] architecture was conducted to optimize parallel processing and implement this architecture on FPGA. It improved the consumption of the power by 90% in compared with others.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

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Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quadengine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image's part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.

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“…The design of the hybrid-redundancy architecture has a pipeline structure based on five stages, where each stage is a set of data processing elements connected in series, which are executed in parallel and filled with the same data blocks in a time-sliced manner for independently computing five results (assuming that these will be equal). In applications where multiprocessors or multi-channels are required—for example, in works developed by Elkabbany et al [ 42 ] and Nabil et al [ 43 ]—a pipeline architecture increases the performance and throughput by processing independent communications lines; in our case, the pipeline architecture is used for processing the same data block, focusing on the detection and correction of errors. For this process, some buffer storage (pipeline registers) is inserted between the five data processing elements, IR&F (Initial Round and Feedback), S&S (SubBytes and ShiftRows), M (Mix Columns), A (Add Round Key), and IC (Intermediate Cipher Data).…”

Section: Proposed Hardware Architecturementioning

confidence: 99%

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Algredo‐Badillo

Ramírez-Gutiérrez

Morales-Rosales

et al. 2021

Sensors

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Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

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Design and implementation of pipelined and parallel AES encryption systems using FPGA

Cited by 12 publications

References 27 publications

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

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