An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

Jeon, D.; Henry, M.; Kim, Yejoong; Lee, Inhee; Zhang, Zhengya; Blaauw, David; Sylvester, Dennis

doi:10.1109/jssc.2014.2309692

Cited by 27 publications

(20 citation statements)

References 22 publications

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“…This supports robust visual comprehension regardless of the position of individual objects in the scene [6]. Being always on even when no event is occurring in the scene, feature extraction dictates the system's minimum power consumption in self-powered vision sensor nodes [3], [7]. Unfortunately, feature extraction accelerators tend to be area-hungry, due to the high degree of parallelism and the large memory required by real-time operation [8]- [11].…”

Section: ])mentioning

confidence: 99%

“…Unfortunately, feature extraction accelerators tend to be area-hungry, due to the high degree of parallelism and the large memory required by real-time operation [8]- [11]. On the other hand, self-powered low-cost vision sensor nodes are required to exhibit very low power and area due to battery life, form factor and cost requirements [3]. Accordingly, vision sensor nodes routinely have moderate resolutions, which are typically around VGA or slightly higher [12].…”

Section: ])mentioning

confidence: 99%

“…Feature extraction is a fundamental task in integrated systems for vision, and is typically the front-end in computer vision systems based on machine learning algorithms [1]. Indeed, feature extraction reduces the dimensionality of compute-intensive vision tasks such as object classification, detection and tracking [2], as mandated in always-on and tightly-constrained computer vision systems [3] (e.g., real-time vision sensor nodes). In such always-on systems, recent deep learning frameworks are well known to be unsuitable, as their power (e.g., tens of mW or more [4…”

Section: Introductionmentioning

confidence: 99%

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Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision

2020

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In this work, an energy-quality (EQ) scalable and memory-frugal architecture for video feature extraction is introduced to reduce circuit complexity, power and silicon area. Leveraging on the inherent resiliency of vision against noise and inaccuracies, the proposed approach introduces properly selected EQ tuning knobs to reduce the energy of feature extraction at graceful quality degradation. As opposed to prior art, the proposed architecture enables the adjustment of such knobs, and adapts its cycle-level timing to reduce the amount of computation per frame at lower quality targets. As further benefit, the approach adds opportunities for energy reduction via aggressive voltage scaling. The proposed architecture mitigates the traditionally dominant area/energy of the on-chip memory by reducing the number of pixels stored on chip, introducing memory access reuse and on-the-fly computation. At the same time, EQ tuning preserves the ability to conventionally operate at maximum quality, when required by the task or the visual context. A 0.55 mm 2 testchip in 40nm exhibits power down to 82µW at 5fps frame rate (i.e., 33X lower than prior art), while assuring successful object detection at VGA resolution. To the best of the authors' knowledge, this is the first feature extractor with sub-mW operation and sub-mm 2 area, making the proposed approach well suited for tightly power-constrained and low-cost distributed vision systems (e.g., video sensor nodes).

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confidence: 99%

Section: ])mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision

2020

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“…In the last decades, several hardware solutions based on these algorithms are proposed to meet the real-time processing requirement. Although some works [5][6] [7] achieve real-time processing, they mostly focus on images with low resolutions, such as VGA (640x480), 512x512 or even lower. With the increasing demand of higher resolution image from visual applications, the faster feature extraction accelerators with lower memory load are required.…”

Section: Introductionmentioning

confidence: 99%

“…It achieves at least 135 A 135 fps 1080p 87. 5 In general, the contributions of this work can be summarized as follows:…”

Section: Introductionmentioning

confidence: 99%

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Zhu

Liu

Jiang

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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Binary image descriptors, which derive image feature description from the local image patches directly, are widely adopted in the mobile and embedded applications due to lower computational complexity and memory requirement. With the aim of improving the computation efficiency without degrading recognition performance, a light-weight binary robust descriptor (L-BIRD) is proposed based on the analysis of the state-of-the-art binary descriptors in this paper. A directional edge detection and optimized keypoint score function are developed to refine the keypoints. In addition, rotation invariance is achieved by executing a circular symmetric based descriptor generation and a coarse-grained orientation calculation method concurrently. Experimental results demonstrate that the proposed keypoint detector and binary descriptor achieve more than 2 times speedup and at least 23.6% improvement in processing speed with comparable performance respectively. Furthermore, a VLSI architecture is also designed based on in-depth exploration of bit-level and task-level parallelism. Based on the post-layout simulation in TSMC 65 nm CMOS process, the accelerator can achieve 135 frames per second (fps) on 1080p image while only consuming 87.5 mW at 200 MHz operating frequency.

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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Abdel‐hafeez

Gordon‐Ross

2021

Circuit Theory & Apps

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We present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications.

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An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

Cited by 27 publications

References 22 publications

Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision

Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

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