An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

Abstract

In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultra-low power accelerators for near-sensor processing. We present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art predication approaches. To optimize the performance and energy efficiency, we explore the IPA architecture with special focus on shared memory access, with the help of the flexible compilation flow presented in this paper. We achieve a maximum energy gain of 2×, and performance gain of 1.33× and 1.8× compared with state of the art partial and full predication techniques, respectively. The proposed accelerator achieves an average energy efficiency of 1617 MOPS/mW operating at 100MHz, 0.6V in 28nm UTBB FD-SOI technology, over a wide range of near-sensor processing kernels, leading to an improvement up to 18×, with an average of 9.23× (as well as a speed-up up to 20.3×, with an average of 9.7×) compared to a core specialized for ultra-low power near-sensor processing.

Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs

“…Comparing with the CPU, the context aware mapping achieves an average of 14× (with a maximum of 23× and minimum of 5×) energy gain. In [1], it is reported that the basic mapping approach combined with the target CGRA with HOM64 configuration achieves leadingedge energy efficiency, surpassing by more than one order of magnitude other state of the art architectures.…”

“…The article [1] describes an efficient solution for the basic mapping problem. The basic approach takes the CGRA TEDG and CDFG as the inputs.…”

“…Some tiles contain a load/store unit for reading and writing back data in the data memory through a logarithmic interconnect. The target CGRA is similar to the one in [1].…”

“…The content of the context memory is made of three kinds of instructions: an operation (including control), a move, or a nop (no operation). Consecutive nops are gathered in one programmable nop (pnop) as presented in [1]. In this context, a mapping tool is thus facing two opposing goals: (1) introducing graph transformations in order to find a valid solution, thus increasing the number of operations, moves and nops, and (2) reducing the number of total instructions to make the contexts fit in the memory of each tile.…”

“…The mapping approach must travel each basic block, and for each block, it must find a valid mapping of the dataflow graph. The way the control flow and the data flow are traversed has an influence on the quality of the resulting mapping [1], [2]. When a valid mapping is found, the compiler generates the assembly code for each tile, which will be placed in the context memory.…”