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Abstract-A preliminary study by Sneddon et al. (2005) using visual working memory tasks coupled with quantified EEG (qEEG) analysis distinguished mild dementia subjects from normal aging ones with a high degree of accuracy. The present study hypothesizes that a simpler task such as having a subject count backwards mentally by ones can be coupled with qEEG to yield a similar degree of accuracy for classifying early dementia. The study focuses on participants with mild cognitive impairment (MCI) and includes both a delayed visual match-tosample (working memory) task and a counting backwards task (eyes closed) for comparison. The counting backwards protocol included 15 normal aging and 11 MCI participants, and the working memory task included 9 normal aging and 7 MCI individuals. The EEG data were quantified using Tsallis entropy, and the brain regions analyzed included the prefrontal cortex, occipital lobe, and the posterior parietal cortex. The

In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultra-low power accelerators for near-sensor processing. We present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art predication approaches. To optimize the performance and energy efficiency, we explore the IPA architecture with special focus on shared memory access, with the help of the flexible compilation flow presented in this paper. We achieve a maximum energy gain of 2×, and performance gain of 1.33× and 1.8× compared with state of the art partial and full predication techniques, respectively. The proposed accelerator achieves an average energy efficiency of 1617 MOPS/mW operating at 100MHz, 0.6V in 28nm UTBB FD-SOI technology, over a wide range of near-sensor processing kernels, leading to an improvement up to 18×, with an average of 9.23× (as well as a speed-up up to 20.3×, with an average of 9.7×) compared to a core specialized for ultra-low power near-sensor processing.

Coarse-Grained Reconfigurable Architectures (CGRAs) are promising high-performance and power-efficient platforms. However, their uses are still limited because of the current capability of the mapping tools. This paper presents a new scalable efficient design flow to map applications written in high level language on CGRAs. This approach leverages on simultaneous scheduling and binding steps respectively based on a heuristic and an exact method stochastically degenerated. The formal graph model of the application, obtained after compilation, is backward traversed and dynamically transformed when needed to allow for a better exploration of the design space. Results show that our approach is scalable, finds most of the time the best solutions i.e. the mappings with the shortest latencies, achieves lowest failure rate in carrying out solutions, provides lower computation time and explores more efficiently the solution space than the state of the art methods.