An energy efficient multipliers using reversible gates

Abstract

The known advantages of Reversible gates namely reduced power consumption and low latency found useful in Quantum computing. Its low power consumption and quicker operation makes them to be useful in applications Microprocessors, DSP processors and Quantum computers. Numerous reversible gates have been found in literature. This article focuses the implementation of 4 bit multiplier with the help of reversible logic gates. Array multiplier is chosen for our choice. Toffoli gate is chosen for partial product generation. The accumulation of partial products is carried using three topologies. The first topology uses reversible carry look ahead adder. The second topology uses parity preserving reversible carry look ahead adders. The third topology uses modified parity preserving reversible carry look ahead adders. The energy efficient multiplier’s topology proposed in this article implementation are done using Cadence 180nm technology. Performance evaluation reveals that the proposed reversible gate based multiplier results lesser power consumption and also a quicker one. It results that the proposed topology consumes 52.03% lesser power, topology 2 consumes 63.02% lesser power and topology 3 consumes 63.79% lesser power when compared with an existing reversible multiplier design. As the power consumption is the dominating quantity in VLSI design, the proposed topologies of multiplier design results better performance. The achieved area occupation of the proposed topology 1, topology and topology 3 are also 58.44%, 61.90% and 69.26% lesser respectively when compared with that existing reversible multiplier. Its quicker operation is also achieved by the reduction in propagation delay. Hence the proposed multiplier topologies named as an energy efficient multipliers.

State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing

“…Ariafar, Z., et al [38], proposed 4-bit efficient reversible multipliers using Vedic mathematics. The first design does not have parity-preserving, while the second design has the capability of parity preserving [39]. Rashno, M., et al [40] introduced four 2-bit r Vedic multiplier blocks using reversible logic, partial products are generated over vertical and cross multiplication.…”

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

“…Signal integrity: Reversible logic gates often exhibit lower fan-out and reduced signal propagation delays compared to irreversible gates [10]. These characteristics can help maintain better signal integrity and alleviate some of the challenges related to interconnect delays, crosstalk, and power supply noise.…”