An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors

Abstract

With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance challenges of 2D integration and the memory wall. However, the 3D design of SRAM LLCs has made the thermal problem even more severe. It, therefore, incurs more leakage energy consumption than conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose two different architectures that exploit the data compression to reduce the energy of LLC and interconnects in 3D-ICs. The fundamental idea of the proposed architectures is to use the non-uniform distribution of the accesses, invalid lines, zero-value lines, and frequent-value (FV) lines in banks of an LLC for decreasing both dynamic and leakage energy. The proposed architectures based on nonuniform cache architectures (NUCA) disable cache banks with low accesses and high invalid, zero, and FV lines, leading to high energy efficiency.

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

“…So, researchers come up with different solutions to deal with these limitations, from redesigning the conventional data structures to proposing hardware-level methods, to deploy these new technologies in their systems. Among all the challenges that Energy efficiency [4,9,13,18,[23][24][25][26][27]35] [41, [65][66][67][68][69][70][71] [ [72][73][74][75][76][77][78] NVMs face, in this paper, we focus on (1) low endurance, high energy consumption, and asymmetric read/write related problems and (2) how researchers in different communities, from databases to storage systems to embedded systems and distributed systems, overcome these limitations. Table 3 classifies the research studies from Table 2 based on their memory technologies.…”

“…So, in PCMs, there are two main operations: SET operation and RESET operation. These operations are controlled by electrical current as follows: while in the RESET operation High-power are used to place the memory cell into the high-resistance RESET state, for the SET ReRAM [8-11, 17, 18, 29, 66, 72, 75, 76] STT-RAM [8,[11][12][13][14][31][32][33] [ 41,42,63,65,70,73] NAND Flash [15,16,28,37,45,46,49] [ 51,54,56,61,64] 3D XPoint [25-27, 38, 40, 43, 44, 47, 48, 50] [ 51, 52, 55, 57-60, 62, 69] operation, moderate power but longer duration pulses are used to return the cell to the low-resistance SET state. Although PCM scales well and has write endurance comparable to that of NAND Flash (10 8 -10 9 ), which makes it a viable alternate for future high-speed storage devices.…”

A Comprehensive Review on Processing-in-Memory Architectures for Deep Neural Networks

“…It discusses the increased attack surface due to the growth of AI capabilities and explores adversarial attacks, model stealing attacks, and concerns regarding privacy and data leakage. Finally, the review concludes by emphasizing the potential of PIM techniques in revolutionizing deep learning hardware and contributing to the development of efficient AI hardware [32].…”

Filter router: An enhanced router design for efficient stacked shared cache network

“…Although many recent researches discover that stacked architectures are greatly adapted in area saving, network interconnection and layout optimization [8,21], however, those architectures are limited in their ability to match locality distributions among applications, and to manage highly shared data efficiently as each application contains different behaviors on runtime system latency, performance and energy debit [29]. Moreover, situations are more critical in shared last level cache, because the shared cache should serve too many threads for many data sharing, resulting in serious efficiency and coherence problems [15,17,26].…”