2013
DOI: 10.1109/jstqe.2012.2224096
|View full text |Cite
|
Sign up to set email alerts
|

An Energy-Efficient Optically Connected Memory Module for Hybrid Packet- and Circuit-Switched Optical Networks

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1

Citation Types

0
14
0
2

Year Published

2014
2014
2022
2022

Publication Types

Select...
7
3

Relationship

0
10

Authors

Journals

citations
Cited by 29 publications
(16 citation statements)
references
References 19 publications
0
14
0
2
Order By: Relevance
“…If we use the above modulators in the two ends (the send and receive), there will be a complete wavelength mismatch when the temperature drifts by only 14°C (under such a temperature variation, wavelength drift is 1.54 nm > 1.48 nm). 3-D stacked nanophotonics, such as circuit-switched optical interconnection networks on logic, can not only decrease the memory access latency but also can improve the power efficiency [13]; however, the thermal crosstalk between the photonic components and high-power logic circuits presents a potential challenge for 3-D photonics.…”
Section: B Silicon Nanophotonicsmentioning
confidence: 99%
“…If we use the above modulators in the two ends (the send and receive), there will be a complete wavelength mismatch when the temperature drifts by only 14°C (under such a temperature variation, wavelength drift is 1.54 nm > 1.48 nm). 3-D stacked nanophotonics, such as circuit-switched optical interconnection networks on logic, can not only decrease the memory access latency but also can improve the power efficiency [13]; however, the thermal crosstalk between the photonic components and high-power logic circuits presents a potential challenge for 3-D photonics.…”
Section: B Silicon Nanophotonicsmentioning
confidence: 99%
“…The root cause of this problem [9] extends along two primary bottlenecks degrading the overall system performance: the long access time of both static and dynamic electronic Random Access Memories (SRAMs and DRAMs, respectively) and the limited bandwidth of the processor-main memory electrical bus. Towards addressing the limited bandwidth problem of electrical bus, optically interconnected CPU-memory paradigms have been demonstrated, indicating that future processor-main memory systems can leverage optics to increase bandwidth through data parallelism [11]- [13]. On the other hand, the long access times of electronic SRAM circuitry will still persist even though optical bus solutions come at the foreground.…”
Section: Introductionmentioning
confidence: 99%
“…In this effort, SOA-MZIs are expected to constitute key elements due to their proven credentials to offer a powerful generic building block for realizing key-processing functionalities for telecom applications, ranging from chipscale packet routing [2] and signal conditioning up to bitwise logic functions [3]. Similar routing and processing functionalities have already started to be exploited also in today's Manuscript rapidly rising field of optical interconnects [5], introducing an additional necessity to accelerate their integration into more compact structures of higher complexity. The first attempt for integrating multiple SOA-MZIs as generic processing blocks on a single chip was successful within the European Commission funded ICT-MUFINS project [2], where InP-based active components (SOAs) were combined with planar silica waveguides on a silicon board.…”
Section: Introductionmentioning
confidence: 99%