An Energy-Efficient Processor Architecture for Embedded Systems

Abstract

Abstract-We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23× greater than an embedded RISC processor.Index Terms-energy-efficient embedded processor architecture, instruction registers, hierarchical and distributed register organization

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor

“…The interconnect overhead in TTAs can be reduced by interconnect reduction, which is particularly effective in application specific processor design. Using explicit bypassing is an alternative of building explicit datapath architecture [8,[12][13][14]. The bypassing (forwarding) network in a conventional processors is used to reduce data hazard caused by the pipelining.…”

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

“…The two groups are distinguished by the second bit (LRU [1]) of the LRU. The first bit (LRU[0]) distinguishes Way0 and Way1 and the third bit (LRU [2]) distinguishes Way2 and Way3. The 4-way set-associative cache algorithm updating the LRU bits is shown in Table 1.…”

“…If the way is Way2 or Way3, LRU [1] will be set to 0. In the case that Way 2 or Way3 is referenced, LRU [2] is set to 1 or 0. The symbol '-' means the value before the update is kept.…”

“…It is necessary to consider performance improvement and power consumption during a processor design. Although most processors use a delayed branch for normal pipeline operations, pipeline operation delay caused by a delayed branch has become a serious obstacle for improving performance [1][2][3][4].Caches have become the most basic and the most important elements determining the performance of high performance microprocessors with unsatisfyingly limited memory bandwidth provided by the systems. In addition, most of the dynamic power of a processor is dissipated on the clock and data-path related circuits.…”

“…It is necessary to consider performance improvement and power consumption during a processor design. Although most processors use a delayed branch for normal pipeline operations, pipeline operation delay caused by a delayed branch has become a serious obstacle for improving performance [1][2][3][4].…”