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Abstract-Composability means that the behaviour of an application, including its timing, is not affected by the absence or presence of other applications. It is required to be able to design, test, and verify applications independently. In this paper we define composable dynamic voltage and frequency scaling (DVFS) hardware, and composable power management. We ensure that the functional and temporal behaviours of an application are not affected by other applications, even when they are power managed.For dataflow applications with worst-case execution times per task, our power management is also predictable, i.e. guarantees end-to-end real-time requirements, even when the application is mapped on multiple processors that are power managed independently. Our method can be used with various DVFS architectures, such as on-chip and off-chip VF regulators.Our FPGA implementation models a system with multiple tiles, each containing a processor with local memory running a realtime operating system (RTOS) and power management. Tiles are interconnected by a network on chip, and communicate using shared memories. Experiments indicate energy savings of 68% w.r.t. no power management, and 40% w.r.t. power gating only. We also demonstrate composability and predictability on the platform in the presence of power management. I. INTRODUCTION Low energy consumption is important for systems on chip (SOC). Dynamic voltage and frequency scaling (DVFS) is oftenused to trade a linear processor slowdown for a potentially quadratic decrease in energy consumption. This trade-off has been exhaustively addressed for single processors, and for multi-processor SOCs [1], [2]. We propose an architecture that uses existing DVFS hardware to build composable and predictable SOCs running multiple applications.To deal with the complexity of system design and verification, the concept of composability has been advocated [3]-[6] and practised [7]. Behaviours of different applications are independent, to be able to develop, test, verify, and execute applications in isolation before they are integrated to a system. A composable SOC then ensures that applications already integrated do not affect the newly added application, and vice versa.Embedded systems contain a mix of best-effort applications, and those that have (hard or soft) real-time requirements, such as radio pipes, and video and audio decoding. Predictability, or timeliness, is required to guarantee that each application meets its deadlines, while composability ensures that multiple

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It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs) which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% in area with a performance penalty of only 7.1%.