Reduction Operator for Wide-SIMDs Reconsidered

Abstract

It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs) which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% in area with a performance penalty of only 7.1%.

A Low-Energy Wide SIMD Architecture with Explicit Datapath

“…For example, partial histogram merging, row projection (sub kernels in the FFoS application described in Section 3.2), Find Maximal Element in a Vector, and Sum of Vector Elements (categorized as global-to-point kernels in Section 3.2). To efficiently handle these kernels on a wide SIMD with only a circular neighborhood network, we introduced two novel reduction algorithms, pipelined reduction and diagonal access reduction, which do not rely on complex communication networks or any dedicated hardware [29]. The key idea of both approaches is to utilize inter-vector parallelism instead of intra-vector parallelism.…”

“…The experimental results show that using the proposed algorithms, the performance is comparable to the performance when dedicated reduction hardware is equipped. For details please refer to the work of L.Waeijen et al [29].…”

“…This is because kernels with only local communication can be efficiently mapped onto such a design, while kernels with global access will spend a significant amount of cycles on data transfers between PEs that are far apart. To reduce the overall cost of long-distance communication, we introduced two algorithms, pipelined reduction and diago- Table 4 Benchmark kernels and the categories they belong to nal access reduction, which do not rely on complex communication networks or any dedicated hardware [29]. The key idea of both approaches is to utilize inter-vector parallelism instead of intra-vector parallelism, which can be applied to both global-to-point and global-to-global kernels.…”

“…Therefore, when the array becomes larger, there is no communication penalty such as the ones for the max and reduction kernels. As mentioned in the previous sections, to reduce the overall cost of long-distance communication, we introduced two algorithms that exploit inter-vector parallelism instead of intra-vector parallelism [29]. These approaches can also be applied to the global-to-global kernels.…”