An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling

Abstract

Abstract-This paper presents a highly energy efficient alternative algorithm to the conventional workload averaging technique for voltage quantized dynamic voltage scaling. This algorithm incorporates the strengths of the conventional workload averaging technique and our previously proposed Rate Selection Algorithm, resulting in higher energy savings while minimizing the buffer size requirement and improving the overall system stability by minimizing the number of voltage transitions. Our experimental work using the Forward Mapped Inverse Discrete Cosine Transform computation (FMIDCT) as the variable workload computation, nine 300-frame MPEG-2 video sequences as the test data, and a 4-level voltage quantization shows that our algorithm produces better energy savings in all test cases when compared to the workload averaging technique, and the maximum energy saving for the test cases was 23%.

Design and CMOS Implementation of a Low Power System-on-Chip Integrated Circuit

“…In order to decrease the dynamic power, methods such as clock gating, MSV, DVFS have emerged. PG is an effective way to eliminate the power where power gates are designed to switch off the power supply applied to a block of logic when it is not in use [1][2][3][4].…”

Optimal voltage allocation techniques for dynamically variable voltage processors

“…That is, the devices use a low-supply voltage during periods of light workload and at the same time, to satisfy the timing constraints. This is because the amount of energy consumption, E i , for task J i in CMOS circuits typically increases quadratically with the supply voltage, as indicated in Chandrasena et al [2001] and Ishihara and Yasuura [1998] (by simply assuming a fixed supply voltage for the task):…”

“…However, the supply voltage scaling incurs one critical penalty: The voltage reduction increases circuit delay, which is approximately linearly proportional to the supply voltage, since the circuit delay, T d , is expressed as [Chandrasena et al 2001]:…”

Optimal voltage allocation techniques for dynamically variable voltage processors

“…Specifically, the contributions are two folds: (1) For given multiple discrete supply voltages and tasks with arbitrary arrival-time/deadline constraints, we propose a voltage allocation technique which produces a feasible (task) schedule with optimal processor energy consumption; (2) We then extend the problem to include the case in which tasks have non-uniform switched capacitances, and solve it optimally. The technique in (1) is based on the prior results in [5] (which is optimal for continuously variable voltages, but not for discrete ones) and [3] (which is optimal for a single task, but not for multiple tasks), whereas the technique in (2) is based on an efficient linear programming (LP) formulation.…”

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission andor a fee. June 2 4 ,2 where Ri is the total number of cycles required for the execution of task Ji, C, is the average switched capacitance per clock cycle for the task, and V, is the voltage supplied to the task. On the other hand, it should be noted that, in addition to the voltage, the value of E, is affected by the switched capacitance of the task (i.e., Ci in E q .…”