An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript

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“…to encode multi-bit data in a single physical quantity, such as time [7], [8], electrical current [9]- [12], charge [13]- [16],…”

Section: Ieee Journal Of Solid-state Circuitsmentioning

confidence: 99%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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“…We consider an integrate-and-fire model as illustrated in Fig. 6, which is commonly employed in matrix-vector computation [23][22][1] [25] and SNNs [19,17]. The time evolution of the membrane potential represented by the voltage at a capacitor is obtained by Kirchhoff's current law, as follows: where I (min) represents the controllable minimum current, I (level) ij is an integer, and C is the capacitance.…”

Section: Circuit Modelmentioning

confidence: 99%

“…6 to study the mapping of SNNs to circuits. These values of parameters were determined typically from VLSI design based on the approach of time-domain analog computing with transient states (TACT), in which synapse currents were given by field-effect transistors operating in a subthreshold region [22,25]. .…”

Section: Optimal Mapping Of Snns To Circuitsmentioning

confidence: 99%

Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks

Sakemi¹,

Matsukawa²,

Hosomi³

et al. 2021

Preprint

Self Cite

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The spiking neural network (SNN) has been attracting considerable attention not only as a mathematical model for the brain, but also as an energy-efficient information processing model for real-world applications. In particular, SNNs based on temporal coding are expected to be much more efficient than those based on rate coding, because the former requires substantially fewer spikes to carry out tasks. As SNNs are continuous-state and continuous-time models, it is favorable to implement them with analog VLSI circuits. However, the construction of the entire system with continuous-time analog circuits would be infeasible when the system size is very large. Therefore, mixed-signal circuits must be employed, and the time discretization and quantization of the synaptic weights are necessary. Moreover, the analog VLSI implementation of SNNs exhibits non-idealities, such as the effects of noise and device mismatches, as well as other constraints arising from the analog circuit operation. In this study, we investigated the effects of the time discretization and/or weight quantization on the performance of SNNs. Furthermore, we elucidated the effects the lower bound of the membrane potentials and the temporal fluctuation of the firing threshold. Finally, we propose an optimal approach for the mapping of mathematical SNN models to analog circuits with discretized time.

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“…Here, each storage element implements single-bit multiplication, which is a part of a larger operation [5]. By employing different types of arithmetic units in memory cells, various types of IMC architectures were developed in [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]. These works aim to improve energy consumption, speed, and accuracy.…”

Section: Introductionmentioning

confidence: 99%

An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

Akgül,

Karalar

2024

Electronics

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In this paper, a mathematical model for obtaining energy consumption of IMC architectures is constructed. This model provides energy estimation based on the distribution of a specific dataset. In addition, the estimation reduces the required simulation time to create an energy consumption model of SRAM-based IMC architectures. To validate our model with realistic data, the energy consumption of IMC is compared by using NeuroSim V3.0 for the CIFAR-10 and MNIST-like datasets. Furthermore, an application is created with our model to select highest performing quantization mapping based upon the parameters of energy consumption and accuracy.

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An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

Cited by 9 publications

References 36 publications

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks

An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

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An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

Cited by 9 publications

References 36 publications

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks

An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures

Contact Info

Product

Resources

About

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs