An enhanced multilevel algorithm for circuit placement

Abstract

This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering) based on techniques from algebraic multigrid (AMG), and (iii) iterated V-cycles with additional geometric information for aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have been largely retained, and the overall run time remains very competitive. Compared to gordian-l-domino [25] on uniformcell-size IBM/ISPD98 benchmarks, a speed-up of well over 8× on large circuits (≥ 100, 000 cells or nets) is obtained along with an average improvement in total wirelength of about 2%. Compared to Dragon [32] on the same benchmarks, a speed-up of about 5× is obtained at the cost of about 4% increased wirelength. On the recently published PEKO synthetic benchmarks, mPL2 generates surprisingly high-quality placements -roughly 60% closer to the optimal than those produced by Capo 8.5 and Dragon -in run time about twice as long as Capo's and about 1/10th of Dragon's.

Large-scale circuit placement

“…Four state-of-the-art placers from academia and one industrial placer were studied for optimality and scalability: Dragon v.2.20 [Wang et al 2000], Capo v.8.5 [Caldwell et al 2000b], mPL v.2.0 [Chan et al 2003b], mPG v.1.0 [Chang et al 2003a], and QPlace v.5.1.55 [Cadence Design Systems, Inc. 1999]. Experiments with Dragon, mPL, mPG and QPlace were performed on a SUN Blade 750 MHz running SunOs 5.8 with 4GB of memory.…”

“…Placement algorithms in the multilevel paradigm have only recently drawn attention [Sankar and Rose 1999;Chan et al 2000;Chang et al 2003a;Chan et al 2003aChan et al , 2003b. These methods are based on coarsening, relaxation, and interpolation, defined as follows.…”

MARS-a multilevel full-chip gridless routing system

“…The multilevel performance-driven partitioning algorithm HPM [27] produces the best balance of delay and cut size minimization results for circuit partitioning. The multilevel placement algorithm mPL [28] achieves comparable circuit placement quality with the well-known Dragon package [29] with over speed-up on designs with over 200 K movable objects. These successes led us to investigate the application of the multilevel scheme to handling large VLSI routing problems.…”

Constructive benchmarking for placement

“…mPL3 [8] This newer version of the mPL series has a strong tendency to place cells in columns that span the entire core areasee Figure 7(a)(b). While this is an improvement over the previous strategy of packing everything to the left, it still produces highly suboptimal solutions in the same benchmarks as before.…”