Abstract-Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems.

Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature, and improvements by over 10% per paper are still common. Large macros can be handled by traditional floorplanning, but are harder to account fol in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scde to large numbers of objects, especially in terms of solution quality.Wepropose to integrate min-cut placement with fixed-outline 8001 planning to solve the more general placement problem, which includes cell placement, Roorplanning, mixed-size placement and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven. fixed-outline floorplanning is invoked. If the latter fails, we undo an earlier paltitioning decision, merge adjacent placement regions and re-floorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelengthdriven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, we propose that free-shape rectilinear floorplilnning can be used with rough module-area estimates before synthesis.

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The ProblemWe describe the classical floorplanning framework and contrast it to the modern fixed-outline formulation. Classical Outline-Free FloorplanningA typical floorplanning formulation entails a collection of "blocks", which can represent circuit partitions in applications. Each block is characterized by area (typically fixed) and shape-type, e.g., fixed rectangle, rectangle with varying aspect ratio, an L-shape, a T-shape, or a more general rectilinear polygon, etc (such shapes may optimize layouts of special types of circuits, e.g., datapaths). A solution to such a problem, i.e., a floorplan, specifies a selection of block shapes and overlap-free placements of blocks. Depending on shape constraints, a floorplanning formulation can be discrete or continuous. For example, if at least one block is allowed to assume any rectangular shape with fixed area and aspect ratio in the interval ¢ a£ b¤ (where a ¥ b) the solution space is no longer finite or discrete. Multiple aspect ratios can be implied by an IP block available in several shapes as well as by a hierarchical partitioning-driven design flow for ASICs [14,9] where only the number of standard cells in a block (and thus the total area) is known in advance. In many cases, e.g., for row-based ASIC designs, there are only finetly many allowed aspect ratios, but solution spaces containing a continuum are used anyways, primarily because existing computational methods cannot handle such a large discrete solution space directly [9]. We point out that in the classical floorplanning formulations, movable blocks tend to have fixed aspect ratios, but the overall floorplan is not constrained by an outline. While several recent works allow for variable block aspect ratios, the more modern fixed-outline formulation (see below) has not been addressed.Objective functions not directly related to area typically involve a hypergraph that connects given blocks. While more involved hypergraph-based objective functions have been proposed, the popularity of the HPWL (half-perimeter wirelength) function is due to its simplicity and relative accuracy, given that routes are not available. The HPWL objective became even more relevant [9] with the wide use of multi-layer over-the-cell routing in which more nets are routed with shortest paths.A fundamental theorem for many floorplan representations, e.g., [10], says that at least one area-minimal placement can be represented. This does not hold for objectives that include wirelength because none of the optimal solutions may be "packed" which implies than more nets can be routed with shortest paths. 1 For the remaining part of this work, we will be dealing with the area and HPWL objectives only, but even this simplified setting implies multi-objective optimization. Mathematically, best trade-offs are captured by the non-dominated frontier (NDF). Definition: a solution of a multi-objective optimization problem belongs to the non-1 A simple example: blocks B 1 and B 2 , connected by two 2-pin nets to fixed pins P 1 and P 2 . Th...

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool.In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade-off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis.In the context of earlier proposed techniques for mixed-size placement [2], we tune a state-of-the-art recursive bisection placer to better handle regular netlists that offer a convenient way to represent memories, datapaths and random-logic IP blocks. These modifications and better whitespace distribution improve results on recent mixed-size placement benchmarks.